An area-efficient universal cryptography processor for smart cards

Abstract

Abstract-Cryptography circuits for smart cards and portable electronic devices provide user authentication and secure data communication. These circuits should, in general, occupy small chip area, consume low power, handle several cryptography algorithms, and provide acceptable performance. This paper presents, for the first time, a hardware implementation of three standard cryptography algorithms on a universal architecture. The microcoded cryptography processor targets smart card applications and implements both private key and public key algorithms and meets the power and performance specifications and is as small as 2.25 mm 2 in 0.18-m 6LM CMOS. A new algorithm is implemented by changing the contents of the memory blocks that are implemented in ferroelectric RAM (FeRAM). Using FeRAM allows nonvolatile storage of the configuration bits, which are changed only when a new algorithm instantiation is required.

Reconfigurable and scalable security module of active RFID for security-sensitive applications

“…The model numbers we chose are ProASIC3-A3P125 and ProASIC3-A3P250 with both 0.13-ȝm flash-based CMOS technology and 125K, 250K system gates in total respectively, the former was used to play the role of the execution unit to make the experiment results closer to reality, while the latter for verifying. As shown in Table II, with DES, AES, RSA, ECC as the examples at 54.24MHz, which needs a frequency multiplier to match with the standard working frequencies of RFID system, our program's performance is much quicker than the systems using software mode only like [12]. And it is more reconfigurable, more scalable than the ones using hardware mode like [13] and [14] as proved in the previous chapters.…”

“…The improved overall architecture of security module is shown in Figure 3. According to the basic theory of computer architecture, we can see that lots of computing operations, such as XOR, modulo multiplication, permutation, and shift, which often appear in a series of encryption/decryption types [4] , which are shown partially in Table I [10,12] . If these operations can be realized through a specific module using ASIC, so each encryption algorithm can spare this module when used.…”

Secure Extension of FPGA General Purpose Processors for Symmetric Key Cryptography with Partial Reconfiguration Capabilities

“…Sequential algorithms are mostly implemented by general purpose processors (GPP), while parallel functions are implemented by the coprocessor placed inside the same cryptographic module or logic device. This approach is frequent in asymmetric key cryptography [Machhout et al 2010;Sakiyama et al 2007], and also in symmetric key cryptography [Crowe et al 16:2 L. Gaspar et al 2004;Eslami et al 2006]. Some embedded systems that use a processor-coprocessor approach implement both symmetric and asymmetric key algorithms in the same device [Hani et al 2006].…”

Cryptographic Extension for Soft General-Purpose Processors with Secure Key Management

“…In order to fulfill contradictory speed/complexity requirements, sequential algorithms are often implemented using embedded generalpurpose processors, while parallel functions are implemented in coprocessors. This approach is very frequent in asymmetric key cryptography [1], [2], and also in block ciphers (such as AES) hardware implementations [3], [4]. Some embedded systems using processor/coprocessor approach implement both symmetric and asymmetric key cryptography algorithms [5].…”