Abstract-Cryptography circuits for smart cards and portable electronic devices provide user authentication and secure data communication. These circuits should, in general, occupy small chip area, consume low power, handle several cryptography algorithms, and provide acceptable performance. This paper presents, for the first time, a hardware implementation of three standard cryptography algorithms on a universal architecture. The microcoded cryptography processor targets smart card applications and implements both private key and public key algorithms and meets the power and performance specifications and is as small as 2.25 mm 2 in 0.18-m 6LM CMOS. A new algorithm is implemented by changing the contents of the memory blocks that are implemented in ferroelectric RAM (FeRAM). Using FeRAM allows nonvolatile storage of the configuration bits, which are changed only when a new algorithm instantiation is required.

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A differential-capacitance read scheme keeps the plateline voltage constant at ground and begins sensing the stored data immediately after a wordline is raised, hence eliminating the time spent in conventional read schemes in raising the highly capacitive plateline and in charge sharing of the bitlines with the ferroelectric capacitors. The proposed read scheme is used in a 256x128-bit testchip that features both 2T-2C and IT-1C cells in 0.35pm technology. The read scheme achieves a 40% reduction in access time.

This paper presents two circuit implementations for the differential capacitance read scheme (DCRS) in ferroelectric random-access memories (FeRAM). Compared to the conventional read scheme, DCRS achieves a faster read access by activating the sense amplifiers immediately after a wordline is activated. By relying on the capacitance difference instead of the charge difference, DCRS avoids raising the highly capacitive platelines until after the read is complete. We have implemented this scheme in a 0.35-m CMOS+Ferro test chip that includes an array of 256 32 2T-2C cells. The test chip measures an access time of 45 ns at a power supply of 3 V.