A Digit Reversal Circuit for the Variable-Length Radix-4 FFT

Ok, Seung-Ho; Moon, Byung In

doi:10.1109/fgcn.2007.7

Cited by 3 publications

(3 citation statements)

References 3 publications

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“…Memory-based approaches [7], [8] have also been proposed for in-place FFT hardware architectures [9]. For pipelined FFT hardware architectures [10], [11], the bit-reversal of a series of data is calculated using either double buffering strategy [11]- [13] or a single memory in which the memory address is generated in natural and bit-reversal order, alternatively for even and odd sequences [14], [15].…”

Section: Introductionmentioning

confidence: 99%

Efficient Circuit for Parallel Bit Reversal

2016

IEEE Trans. Circuits Syst. II

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Bit-reversal is an essential part of the fast Fourier transform (FFT). However, compared to the amount of works on FFT architectures, much fewer works are dedicated to bitreversal circuits until recent years. In this brief, the minimum latency and memory required for calculating the bit-reversal of continuous-flow parallel data are formulated. The formulas are generic for all power of 2 parallelism including the serial bit-reversal. Furthermore, an efficient circuit for calculating the parallel bit-reversal is proposed. The circuit not only achieves the lowest latency but also uses the minimum memory. This is achieved by breaking the bit-reversal permutation into two sub-permutations, which are implemented by a sub-bit-reversal module and a group of P buffer banks. In addition, two commutators are adopted to access the P buffer banks efficiently. The proposed circuit is simple and efficient for reordering the output samples of parallel pipelined FFT processors.Index Terms-Bit-reversal circuit, fast Fourier transform (FFT), parallel pipelined architecture.

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Section: Introductionmentioning

confidence: 99%

Efficient Circuit for Parallel Bit Reversal

2016

IEEE Trans. Circuits Syst. II

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“…Besides, when radices such as radix-4 or radix-8 are used, the outputs of the FFT are provided in an order different from bit reversal [10]. These cases are also studied and optimum circuits for these radices are obtained.…”

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confidence: 99%

“…For in-place FFT hardware architectures [8] memory-based approaches have also been proposed [9], [10]. They focus on the design of the address generator.…”

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confidence: 99%

Optimum Circuits for Bit Reversal

Garrido

Grajal

Gustafsson

2011

IEEE Trans. Circuits Syst. II

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Abstract-This paper presents novel circuits for calculating the bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have the minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware FFT architectures.The paper also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2 k , radix-4 and radix-8.

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Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures

Chen

Huang

Garrido

et al. 2014

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.

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A Digit Reversal Circuit for the Variable-Length Radix-4 FFT

Cited by 3 publications

References 3 publications

Efficient Circuit for Parallel Bit Reversal

Efficient Circuit for Parallel Bit Reversal

Optimum Circuits for Bit Reversal

Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures

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