Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures

Abstract

Abstract-This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.

An Optimum Architecture for Continuous-Flow Parallel Bit Reversal

“…For parallel pipelined bit-reversing, it is challenging to permutate among multi-path data flows and generate multiple outputs continuously [17]. Based on the algorithms in [18], once the basic circuits for parallel pipelined bit-exchanges are proposed, the whole architecture can be obtained by simply cascading these basic circuits.…”

“…[15] presents optimum circuits for achieving bit reversal with lowest memory and lowest latency but it can only support single-path data. Among the parallel bit-reversing circuits, the circuits in [17] are most general and cost-efficient with memory of size N and lower latency. But [17] can not improve its architecture to further reduce memory size and latency.…”

“…Among the parallel bit-reversing circuits, the circuits in [17] are most general and cost-efficient with memory of size N and lower latency. But [17] can not improve its architecture to further reduce memory size and latency. The proposed architecture in this letter successfully achieve parallel bit reversal with lowest memory and lowest latency.…”

“…The circuits proposed in [5] can only accept specific parallel order. The proposed circuits in [17] consist of two flexible commutators and memory of size N , which is regular and flexible for hardware implementation.…”

Design of an 8-Channel FFT Processor for IEEE 802.11ac MIMO-OFDM WLAN System

“…The data scheduling of the R2SDF computation results is not in natural order for the 8-channel data stream. In MIMO-OFDM systems, FFT processors are generally followed by processing blocks, which require timely input data in natural order [1]. The proposed bit-reversal circuit can convert the output data of the FFT architecture from a non-natural into a natural order.…”