A digital chip timing recovery loop for band-limited direct-sequence spread-spectrum signals

Gaudenzi, R. De; Luise, Marco; Viola, R.

doi:10.1109/26.241756

Cited by 72 publications

(26 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this section, the loop baseband equivalent and the loop equation of the DDLL proposed in Reference [4] (see Figure 1) for a band-limited spread-spectrum demodulator are presented.…”

Section: Model Descriptionmentioning

confidence: 99%

“…The NCO in this loop is a perfect integrator, with g representing the NCO gain. The characteristics of the timing error discriminator ðEÞ, and the error dependent noise intensity S N ðEÞ of the all-digital band-limited DDLL were derived in [4]. The noise w k is a white Gaussian noise i.i.d.…”

Section: Model Descriptionmentioning

confidence: 99%

“…A first order noncoherent all-digital delay lock loop (DDLL) for bandlimited CDMAwas presented in [4]. In this work, the timing jitter variance and the mean time to lose lock (MTLL) for the case without Doppler shift were presented.…”

Section: Introductionmentioning

confidence: 99%

“…Band limitation in a direct-sequence spread-spectrum (DSSS) system was shown to achieve the advantages of CDMA with good spectral efficiency [4][5][6]. A first order noncoherent all-digital delay lock loop (DDLL) for bandlimited CDMAwas presented in [4].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Optimal design of an all-digital chip timing recovery loop for direct-sequence spread-spectrum systems

Hasson

Bobrovsky

2005

Eur. Trans. Telecomm.

View full text Add to dashboard Cite

SUMMARYNoncoherent digital delay lock loops (DDLL) are suited for chip timing synchronisation in band-limited direct-sequence spread-spectrum (DSSS) demodulators. The diffusion approximation and the singular perturbation method are used in this paper to calculate the mean time to lose lock (MTLL) of the DDLL. Loop bandwidth optimisation for first order loop with severe Doppler is presented. A simple design rule for the loop bandwidth and a systematic approach for the loop threshold calculation are presented.

show abstract

“…In this section, the loop baseband equivalent and the loop equation of the DDLL proposed in Reference [4] (see Figure 1) for a band-limited spread-spectrum demodulator are presented.…”

Section: Model Descriptionmentioning

confidence: 99%

Section: Model Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Optimal design of an all-digital chip timing recovery loop for direct-sequence spread-spectrum systems

Hasson

Bobrovsky

2005

Eur. Trans. Telecomm.

View full text Add to dashboard Cite

show abstract

“…There exists a large bibliography for these techniques and their theoretical aspects (e.g., [5,6,19,29,30,[32][33][34][89][90][91][92]). This section proposes a practical approach, focusing on implementation aspects.…”

Section: Tracking Stagementioning

confidence: 99%

Software-Defined Radio Technologies for GNSS Receivers: A Tutorial Approach to a Simple Design and Implementation

Principe

Bacci

Giannetti

et al. 2011

International Journal of Navigation and Observation

View full text Add to dashboard Cite

The field of satellite navigation has witnessed the advent of a number of new systems and technologies: after the landmark design and development of the Global Positioning System (GPS), a number of new independent Global Navigation Satellite Systems (GNSSs) were or are being developed all over the world: Russia's GLONASS, Europe's GALILEO, and China's BEIDOU-2, to mention a few. In this ever-changing context, the availability of reliable and flexible receivers is becoming a priority for a host of applications, including research, commercial, civil, and military. Flexible means here both easily upgradeable for future needs and/or on-the-fly reprogrammable to adapt to different signal formats. An effective approach to meet these design goals is the software-defined radio (SDR) paradigm. In the last few years, the availability of new processors with high computational power enabled the development of (fully) software receivers whose performance is comparable to or better than that of conventional hardware devices, while providing all the advantages of a flexible and fully configurable architecture. The aim of this tutorial paper is surveying the issue of the general architecture and design rules of a GNSS software receiver, through a comprehensive discussion of some techniques and algorithms, typically applied in simple PC-based receiver implementations.

show abstract

Synchronization in Digital Communication Systems

Luise

Mengali

Morelli

2003

Wiley Encyclopedia of Telecommunications

View full text Add to dashboard Cite

Reliable data detection in digital communication receivers requires that the incoming waveform be time‐aligned with certain locally generated references, namely the data clock and the sinusoidal waveforms used for demodulation. Accomplishment of this goal is referred to as synchronization (abbreviated: sync) and represents a crucial issue in the design of communication systems. Inaccurate receiver synchronization has generally catastrophic effects on the communication link performance. In addition, synchronization circuits encompass such a large part of the receiver resources that they heavily affect the overall cost. In the following we present an overview of the main synchronization functions for a large class of digitally modulated signals, including conventional (narrow‐band) modulations, direct‐sequence spread‐spectrum, and multicarrier signals. The different sync functions are split into signal and network synchronization. The former includes data clock and carrier frequency/phase recovery, and is typically carried out within the physical layer of a communication network. The latter is usually performed on digital data streams at the higher layers of the ISO/OSI stack, and deals with the time‐alignment of data frames within the format of the digital stream. As the advent of VLSI technology tends to render obsolete the analog circuits employed so far, this chapter is especially concerned with the description of digital signal processing (DSP)‐based synchronization functions.

show abstract

A digital chip timing recovery loop for band-limited direct-sequence spread-spectrum signals

Cited by 72 publications

References 5 publications

Optimal design of an all-digital chip timing recovery loop for direct-sequence spread-spectrum systems

Optimal design of an all-digital chip timing recovery loop for direct-sequence spread-spectrum systems

Software-Defined Radio Technologies for GNSS Receivers: A Tutorial Approach to a Simple Design and Implementation

Synchronization in Digital Communication Systems

Contact Info

Product

Resources

About