A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery

Abstract

This paper presents a digital PLL for low long-term jitter clock recovery. A jitter reduction scheme for digitally controlled oscillator is proposed and 39% jitter reduction is observed. A 5-phase digital phase frequency detector (PFD) has 265 ps resolution and controls output clock phase by 132 ps step. The long-term jitter is measured as 460 ps pk-pk. This digital PLL is implemented in 0.18 µm CMOS process using 0.417 mm 2 and consumes 61.0 mW power.