A direct method for the calculation of the edge capacitance of thick electrodes

Abstract

A new method is presented for the evaluation of the edge-capacitance correction for electrodes of finite thickness. The corrections are divided into three separate components: electrode thickness, the lower edge of the electrodes, and the back of the electrodes. Simple correction formulae are derived for the first two components and a set of curves is provided which enables the direct evaluation of the third component from an equally simple formula. Numerical results show excellent agreement with those obtained by more tedious graphical methods.

Comparison of the RF MEMS switches with dielectric layers on the bridge’s lower surface and on the transmission line

“…As described in [15], C 2 and C 3 mainly depend on the thickness of the narrow electrode and the distance between two electrodes. Although ref.…”

“…The cross-section diagram of RF MEMS switch in x and y directions can be considered as two asymmetrical parallel-plate capacitors with different widths of upper and lower electrodes. The fringing capacitance of this asymmetrical parallel-plate capacitor was first calculated by Kamchouchi and Zaky [15], which was for two circular plates with different dimensions. In their method, the edge capacitance of two disc electrodes was separated into three different regions ( Figure 4): the lower corner (C 1 ), the vertical edge (C 2 ), and the back of the electrodes (C 3 ), calculated by…”

“…Although ref. [15] was for the fringing capacitance of circular plates, the analysis and calculations did not characterize the circle but were deduced to calculate the capacitances in unite length. Therefore, the formulas are also suitable for infinite or considerably long rectangle parallel-plate capacitor with different plate widths.…”

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

“…The total fringe capacitance can be obtained by multiplying (3) with the perimeter of the bottom edge of the gate electrode [3]. Since we need to account for electric field lines fringing from the bottom edge of the gate to either the source or the drain region only, the internal fringe capacitance can be written as…”

“…Kamchouchi and Zaky [3] developed a model for the parasitic capacitance associated with the bottom edge of the gate electrode in which it is assumed that (i) the dielectric is the same throughout and (ii) its thickness (t ox ) is much less than the gate length (L g ). However, in scaled down MOSFETs, the gate dielectric and the spacer oxide have different permittivities.…”