Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

Kumar, M. Jagadesh; Gupta, Santosh Kumar; Venkataraman, Vivek

doi:10.1109/ted.2006.870424

Cited by 41 publications

(22 citation statements)

References 9 publications

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“…Using (13) is equivalent to make the assumption that the electric field in the oxide cross normally the oxide/channel interface (note that this assumption was also used in [9]). This is not the case at the edges of the channel, where there is a strong fringing field, especially when a thick oxide with a high-κ material is used [23]. The value of the elliptic modulus for the inner fringe capacitance k if is now discussed.…”

Section: Inner Fringe Capacitancementioning

confidence: 98%

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Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Hiblot

Rafhay

Bœuf

et al. 2015

IEEE Trans. Electron Devices

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In this paper, the main MOSFET parasitic capacitances of planar devices (i.e., bulk, Fully depleted silicon-on-insulator (FDSOI), and planar double gate) are computed using two successive conformal mapping transforms. First, the structure is mapped to the real axis of the complex plane, and then the second transform, deduced directly from the Schwarz-Christoffel theorem, reduces the capacitance to the trivial parallel electrodes case. This second step involves elliptic integrals, which provide a generic expression for all parasitic capacitances. This method is later compared against other models based on conformal mapping. Finally, the results are validated with finite-element method simulations of the inner and outer fringe capacitances in different architectures, including metallic contacts and raised and faceted junctions.Index Terms-CMOS, compact model, conformal mapping, electrostatic, elliptic integrals, Model for Assessment of CMOS Technologies and Roadmaps (MASTAR), MOSFET, parasitic capacitance, roadmap.

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Section: Inner Fringe Capacitancementioning

confidence: 98%

“…It should be noted that the introduction of high-κ materials with thick oxide thicknesses have induced additional parasitic capacitances, due to field lines crossing the oxide and the spacer [23], [24]. This case was not considered here.…”

Section: Inner Fringe Capacitancementioning

confidence: 99%

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Hiblot

Rafhay

Bœuf

et al. 2015

IEEE Trans. Electron Devices

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“…[32][33][34] At the source side, source depletion in the bulk TFET occurs due to the source-channel electric field and gate-source fringe electric field. The approximation of full depletion is adopted to solve the source depletion charge and relevant capacitance Q s;dep ¼ ÀqN s L 1 X j W g ;…”

Section: B Modeling Of Charges and Terminal Capacitancesmentioning

confidence: 99%

A closed-form capacitance model for tunnel FETs with explicit surface potential solutions

Wang

Huang

et al. 2014

Journal of Applied Physics

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General analytical Poisson solution for undoped generic two-gated metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 90, 012110 (2007);In this paper, a closed-form physical capacitance model for bulk tunnel FETs (TFETs) is proposed based on the surface potential approach for the first time. Fundamentally different from that in the MOSFET, the channel surface potential u sf in the TFET is alternately controlled by the drain bias and gate bias in different operation regions. On the basis of physical insight into the operation mechanism, the analytical model of u sf as a function of terminal bias is established. The Gaussian box is introduced to predict the surface potential profile near the source-body junction. Furthermore, the surface-potential-based capacitance model is derived and the calculated terminal capacitances show good agreement with the TCAD simulation results. With the essential physics considered, excellent validity of the model is achieved for bulk TFETs with a large range of structure parameters and SOI/double-gate (DG) TFETs. V C 2014 AIP Publishing LLC.

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“…The use of high K materials [13][14] as gate oxide results in to the increase in on state current while off state current, subthreshold slope and DIBL decreases, enhancing the FinFET performance due to the fringing electric field [15]. The magnitude of the fringing electric field depends upon the dielectric constant of the medium in which it is getting leaked.…”

Section: Effect Of High K Dielectric Materials On Gaa Structurementioning

confidence: 99%

High Fin Width Mosfet Using Gaa Structure

Tripathi¹

2012

VLSICS

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This paper describes the design and optimization of gate-all-around (GAA) MOSFETs structures. The optimum value of Fin width and Fin height are investigated for superior subthreshold behavior. Also the performance of Fin shaped GAA with gate oxide HfO2 are simulated and compared with conventional gate oxide SiO2 for the same structure. As a result, it was observed that the GAA with high K dielectric gate oxide has more possibility to optimize the Fin width with improved performance. All the simulations are performed on 3-D TCAD device simulator.

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Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

Cited by 41 publications

References 9 publications

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

A closed-form capacitance model for tunnel FETs with explicit surface potential solutions

High Fin Width Mosfet Using Gaa Structure

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