The impact of metal gate work function on the device performance of 22 nm Double-gate FinFET with Si02 and high-k gate oxide LaAI03 is studied over a wide range of work functions. Matlab is used to calculate equivalent oxide thickness of high-k material LaAI03 and simulations are carried out in PADRE device simulator. Quantum-mechanical effects such as Band to Band Tunnelling, Band Gap Narrowing, Carrier-Carrier Scattering are taken care of in the simulation by including the nonlinear drift velocity model and Lombardi's transverse field dependent mobility model. We propose a novel device with high k LaAI03 and the metal gate TiN. Our results show improvement in on-current, transconductance and degradation in the short channel effects DIBL and subthreshold swing. Using matlab the effect of fin width and underlap length on the fringing capacitance of DG-FinFET is also simulated. To achieve low leakage, optimizations of fin width and underlap length are done via simulations. From our results we propose that a fin width in the range of 6nm-8nm and an underlap length of 3nm are suitable for the novel DG-FinFET structure at 22nm gate length with high-k LaAI03 and metal gate TiN. Keywords-DG-FinFET, high-k,metal gate,jin width,/ringing capacitance LINTRODUCTION To scale the planar bulk MOSFET into nanometres regime, significant challenges and difficulties come across to control the SCEs. Non planar three-dimensional devices with multiple gates are more promising candidate for high current drive capability and better short-channel characteristics [6]. The use of ultra-thin body (UTB) and Multiple Gate SOl structures allows the fabrication of fully-depleted devices that offer not only extremely good control of SCEs but also a very good behaviour with respect to drain induced barrier-height lowering (DIBL), threshold voltage roll-off, and off-state leakage [7]. DG-FinFET is one of the examples of non planner multi-gate MOSFET with superior performance than planner DG MOSFET [5]. Intel's 22nm CMOS node is the 1st commercially available bulk-FinFET technology and opens a new era of 3D CMOS for the low-power mobile electronics and continuously driving CMOS scaling and Moore's law.Metal gates together with the high-k dielectrics are considered