A DSP-based hearing instrument IC

Neuteboom, H.; Kup, B.M.J.; Janssens, M.

doi:10.1109/4.641702

Cited by 102 publications

(41 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Then the required minimum supply voltage is the voltage of a forward-biased base-emitter junction plus a headroom for a current source. Thus, the circuit can be realized with a supply voltage around 0.9 V. Such circuits have been reported in [216,217,218,219].…”

Section: Low Voltage Bgr Circuitsmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

View full text Add to dashboard Cite

The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

show abstract

Section: Low Voltage Bgr Circuitsmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

View full text Add to dashboard Cite

show abstract

“…Similar to Neuteboom et al [5], Banba et al [6] have also proposed a technique to overcome these limitations to implement sub-1 V bandgap voltage reference circuits in CMOS technology. They have used resistive sub-division technique to reduce the minimum required supply voltage.…”

Section: Banba's Voltage Reference: 1999mentioning

confidence: 99%

Survey of Bandgap and Non-bandgap based Voltage Reference Techniques

Hande

Baghini

2016

Scientia Iranica

View full text Add to dashboard Cite

Abstract. The design challenges of voltage reference generators in CMOS technology have increased over the years in low-voltage low-power CMOS integrated circuits, constituting analog, digital, and mixed-signal modules. The emergence of hand-held power autonomous devices pushes the power consumption limit to nW regime. Along with these confrontations, limited full-scale range of data converters at low supply levels demands accurate reference voltage generators. This paper reviews the allied design challenges and discusses the evolved methodologies to tackle them. This paper also prominently surveys the sub-1 V voltage reference topologies presented in the literature along with classic bandgap based voltage reference topologies. Non-bandgap (only CMOS) based reference architectures are proven to be area-and power-e cient, but always have to be accompanied with auxiliary on/o chip trimming mechanism for high accuracy. We also provide insightful analysis of the voltage reference topologies required by the designers.

show abstract

“…According to this requirement, the development of the digital hearing aid system with low power consumption, more flexibility, small form factor and low cost is getting to achieve much attention. The previous studies had accomplished low power hearing aid system by adopting special CMOS process such as low-threshold voltage [6] or by using a log-domain analog hearing aid with sub-threshold technique [7]. However, those approaches have some weaknesses to reduce power dissipation because of boosted supply voltage for analog blocks or signal processing with analog filters which dissipates high power.…”

Section: Introductionmentioning

confidence: 99%

A Sub 1V 96 ¿W Fully Operational Digital Hearing Aid Chip With Internal Status Controller

Kim¹,

Cho²,

Song³

et al. 2006

2006 Proceedings of the 32nd European Solid-State Circuits Conference

View full text Add to dashboard Cite

Abstract-A Low power fully operational digital hearing aid chip is proposed and implemented. The Σ-∆ ADC adopts the status controller to realize adaptive SNR technique without any external control. To achieve both low power consumption and high programmability, dedicated low power DSP with 6 control parameters is designed. The heterogeneous Σ-∆ DAC reduces more power dissipation without performance degradation. The digital hearing aid system is fabricated in 0.18 µm CMOS technology, consumes less than 96 µW and has a die size of 2.8 mm x 1.1 mm.

show abstract

A DSP-based hearing instrument IC

Cited by 102 publications

References 14 publications

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Survey of Bandgap and Non-bandgap based Voltage Reference Techniques

A Sub 1V 96 ¿W Fully Operational Digital Hearing Aid Chip With Internal Status Controller

Contact Info

Product

Resources

About