A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture

Fujii, Takayoshi; Furuta, K.; Motomura, Masato; Nomura, Michio; Mizuno, Masayuki; Anjo, K.; Wakabayashi, Keiji; Hirota, Y.; Nakazawa, Yasuhiro; Ito, H.; Yamashina, M.

doi:10.1109/isscc.1999.759297

Cited by 48 publications

(13 citation statements)

References 5 publications

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“…This has started to change and new architectures are proposed. In [6,12], the proposed architecture can store up to 8 different contexts to configure LUTs with a fast hardware context switch. In [11] a similar architecture with 8 different contexts is presented along with a scheduling algorithm to partition a technology mapped design.…”

Section: Related Researchmentioning

confidence: 99%

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High-level synthesis with reconfigurable datapath components

Economakos

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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High-level synthesis is becoming more popular as design densities keep increasing, especially in the ASIC design world. Although FPGA design follows ASIC design methodologies and FPGA densities are increasing too, programmable devices also offer the advantage of partial reconfiguration, which allows an algorithm to be partially mapped into a small and fixed FPGA device that can be reconfigured at run time, as the mapped application changes its requirements. This paper presents a novel resource constrained high-level synthesis scheduling heuristic, which utilizes reconfigurable datapath components. The resulting schedule can be shortened so as the gain in clock cycles can overcome the timing overhead of reconfiguration. The main advantage of the proposed methodology is that through run time reconfiguration, more complicated algorithms can be mapped into smaller devices without speed degradation.

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Section: Related Researchmentioning

confidence: 99%

“…The reconfiguration data can be stored inside the reconfigurable device [10] or transfered from an embedded or host processor [9]. The underlying architecture can be traditional FPGAs or special purpose architectures [6,11,12], supporting very fast reconfiguration.…”

Section: Introductionmentioning

confidence: 99%

High-level synthesis with reconfigurable datapath components

Economakos

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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“…DRL from NEC [101] is a fine-grained multi-context partially reconfigurable FPGA. It contains an array of logic blocks (LBs), an address decoder and I/O selectors.…”

Section: Commercially Available Fpgas Designed For Efficient Run-timementioning

confidence: 99%

Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Shoa

Shirani

2005

J VLSI Sign Process Syst Sign Image Video Technol

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Today's digital signal processing (DSP) applications use computationally complex and/or adaptive algorithms and have stringent requirements in terms of speed, size, cost, power consumption, and throughput. Efficient hardware implementation techniques should be employed to meet the requirements of these applications. Run-Time Reconfiguration (RTR) is a promising technique for reducing the hardware required for implementing DSP systems as well as improving the performance, speed and power consumption of these systems. In this survey, we explain different issues in run-time reconfigurable systems and list the implemented systems which support run-time reconfiguration. We also describe different applications of run-time reconfiguration and discuss the improvements achieved by applying run-time reconfiguration.

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“…Several such devices have been proposed over the years which include [2], [3], [8], [9], [12], [17], and [20]. However, they require an application to be partitioned temporally subject to some new conditions not present in the traditional spatial partitioning problem.…”

Section: Introductionmentioning

confidence: 99%

Temporal logic replication for dynamically reconfigurable FPGA partitioning

Mak

Young

2002

Proceedings of the 2002 International Symposium on Physical Design

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Abstract-In this paper, we propose the idea of temporal logic replication in dynamically reconfigurable field-programmable gate array partitioning to reduce the communication cost. We show that this is a very effective means to reduce the communication cost by taking advantage of the slack logic capacity available. Given a -stage temporal partition, the min-area min-cut replication problem is defined and we present an optimal algorithm to solve it. We also present a flow-based replication heuristic which is applicable when there is a tight area bound that limits the amount of possible replication. In addition, we show a correct network flow model for partitioning sequential circuits temporally and propose a new hierarchical flow-based performance-driven partitioner for computing initial partitions without replication.

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A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture

Cited by 48 publications

References 5 publications

High-level synthesis with reconfigurable datapath components

High-level synthesis with reconfigurable datapath components

Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Temporal logic replication for dynamically reconfigurable FPGA partitioning

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