A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells

Abstract

Nowadays, design issues related to physical design and scalability are becoming the main bottlenecks of modern tools for technology mapping, limiting the usage of large cells. On the other hand, the generation of regular macro cells, such as compound gates, are becoming interesting from the manufacturing point of view, but they need to be properly integrated into the existing industrial design flows. In this paper, we present an efficient methodology for identifying the cells that can extend an existing standard-cell library. We validated our approach on different benchmarks targeting area minimization and we also analyzed timing, power consumption and routing effects for the final circuit implementation

Efficient testing of multi‐output combinational cells in nano‐complementary metal oxide semiconductor integrated circuits

“…This approach has been implemented in a serial fault simulator targeting a single cell b at a time. During the simulation of the test sequence T, as soon as configuration ξ occurs at the inputs of b, the fault simulator incrementally updates Δ(b, ξ) accordingly to (3). A PPIs configuration ξ is dropped when Δ(b, ξ)∨f b (ξ) becomes 1 (i.e.…”

“…The integrated circuit (IC) community expects a growing adoption of complex combinational cells, in addition to standard, fully complementary CMOS gates, an evolution mainly driven by three factors: (i) the increasing complexity of CMOS cells, now providing such complex components as area‐optimised full‐adders [1, 2] and other functions by exploiting pass‐transistor logic and non‐complementary CMOS design [3]; (ii) the use of CMOS logic modules (often called bricks [4] in this context) featuring a regular layout structure to reduce the problems due to litography reliability; and (iii) the future device nanofabrics implementing logic bricks [5] or programmable logic array (PLA)‐like structures [6].…”

A design methodology for the automatic sizing of standard-cell libraries

“…Moreover, the size of the target library has to be known in advance and the algorithm stops when this limit is reached, potentially leading to suboptimal solutions. On the other hand, [11] efficiently identifies the Boolean functions that are not contained into the initial library and can improve the synthesis. However, all variants are generated for each new function, greatly enlarging the size of the library and thus the design space for the technology mapping.…”

“…For this reason, different EDA vendors offer tools (e.g., Synopsys Cadabra, Prolific ProGenesis and Nangate Library Creator) for the automatic generation of optimized CMOS complex gates. As a result, introducing new cells, along with dedicated technology variants, has been demonstrated [8,11] to introduce significant improvements in terms of area, timing and power consumption. However, this introduces additional issues for the design of cell libraries, since these cells need to be accurately selected and properly generated.…”