A fast-locking phase-locked loop using CP control and gated VCO

Lee, Ivan; Tsai, Yun-Ta; Liu, Shen-Iuan

doi:10.1109/vlsi-dat.2012.6212601

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Tradeoffs between settling time and jitter in phase locked loops

Paliwal

Laad

Sattineni

et al. 2013

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

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In most PLL architectures, trade-off exists between settling time and jitter performance, which is ignored during Figure of Merit calculation. This work derives a new Figure of Merit for PLL, which has settling time as added performance parameter, along with jitter and power. Here, the trade-off between settling time and jitter is analyzed theoretically, and with behavioral simulations for (i) linear Time-to-Digital based PLL (ii) non-linear Bang-Bang Phase Detector based PLL (iii) Hybrid PLL with adaptive gain, to obtain settling time vs. jitter relation, based on which commonly used Figure of Merit is modified. To understand trade-off relation between settling time and jitter for Bang-Bang Phase Detector based PLL, this work also derives settling time equation for non-linear PLL, by using recursive time-domain equations.

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