A Flexible Design Flow for Software IP Binding in FPGA

Gora, Michael; Maiti, Abhranil; Schaumont, Patrick

doi:10.1109/tii.2010.2068303

Cited by 22 publications

(9 citation statements)

References 31 publications

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“…Therefore, many scholars are studying the applications of FPGA. The application of FPGA technology to industrial control systems [63,64] is one of the hot topics. FPGA is usually used to control the PWM wave in electric drive and power electronics systems [65], so as to build a SoC (system on a chip) [66] and designed fuzzy logic controller [67].…”

Section: Fpga Technology and Its Potential In Scnmentioning

confidence: 99%

A new approach for data processing in supply chain network based on FPGA

Zou

Tao

Jiang

et al. 2015

Int J Adv Manuf Technol

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With the development of the supply chain network (SCN) and big data processing, a simple view at above two technologies separately has become unadvisable; this mainly reflected on the growing amount of data in the SCN nodes. Since the data processing is not timely, the potential risks may spread like dominoes to the entire network. There are many small nodes in the SCN, in which it requires data processing equipment that have characteristics of high integration and miniaturization. For the phenomenon that large shape and real-time shortage exists in designing underlying data processing equipment in SCN with the traditional special large computers and general embedded processor, this paper considering the advantage of parallel character of FPGA (field programmable gate array), a new method, which uses FPGA to design embedded device to execute related algorithms in parallel for underling data processing to reduce risks which caused by time-delay in SCN, is proposed. To verify effectiveness of the proposed method, a FPGAbased design method for Kalman filter algorithm and median filter algorithm is proposed. The performance and advantage of the proposed method are analyzed by comparing with traditional methods. The results shown that the proposed method have high real-time and accuracy in complex algorithm execution for SCN underling data processing, which can reduce the potential risk and improve the performance of entire SCN.

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Section: Fpga Technology and Its Potential In Scnmentioning

confidence: 99%

A new approach for data processing in supply chain network based on FPGA

Zou

Tao

Jiang

et al. 2015

Int J Adv Manuf Technol

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“…One of the three key registers is pre-loaded with the CV's secret key K C V , which is to be used for deriving the secret IP key K IP for IP decryption; the other two registers are empty initially. The secret key K C V is hidden and obfuscated in the routing information of the CIM's bitstream, which is generally believed to be the hardest to reverse accurately [36].…”

Section: B Core Installation Module (Cim)mentioning

confidence: 99%

“…To make the extraction task harder for the MA, K C V j is proposed to be hidden in the routing information of CIM's bitstream as in [36]. Alternatively, white-box block ciphers [37], [38], which can protect the embedded secret key through strong obfuscation, can be used as the decryption engine of CIM to raise the barrier of successfully extracting the key.…”

Section: B Possible Security Enhancementsmentioning

confidence: 99%

A Pragmatic Per-Device Licensing Scheme for Hardware IP Cores on SRAM-Based FPGAs

Zhang

Chang

2014

IEEE Trans.Inform.Forensic Secur.

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The modus operandi of the upfront intellectual property (IP) licensing model is impractical for the developers of small to medium volume of field-programmable gate array (FPGA)-based applications. The FPGA IP market is in dire need for a more competitive and secure IP licensing scheme to flourish. In this paper, a pragmatic security protocol that could support the licensing of IP cores on a per-device basis without the need for a contractual agreement of an external trusted third party, large bandwidth, and complicated flow of communications is proposed. Besides assuring that the incentives of all stakeholders involved in the FPGA IP core trading are not scarified if not enhanced, the proposed protocol guarantees total secrecy and integrity of licensed IP cores based on available primitives of contemporary SRAM-based FPGA devices. It also prohibits the implementation of protected IP cores on unscreened excess devices and counterfeit chips sold in the gray market. The adoption of IP fingerprinting further deters the IP licensees from abusing the IP cores. Using the self-reconfiguration feature of FPGAs today, the resources consumed by the control module used for the implementation of protected IP cores on the authorized device are temporary and marginal.

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“…This also entails integrating FPGA-related development tasks in the product development flow so as to limit toolchain complexity and reduce engineering costs over the whole product lifetime [10], [11]. One particular research topic has been the use of reconfigurable fabrics (e.g., FPGAs) to accelerate execution of general purpose applications in embedded scenarios [12], [13].…”

Section: Related Workmentioning

confidence: 99%

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

Bispo

Paulino

Cardoso

et al. 2013

IEEE Trans. Ind. Inf.

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This paper presents a novel approach to accelerate program execution by mapping repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable array of functional units. An offline tool suite extracts Megablocks from microprocessor instruction traces and generates a Reconfigurable Processing Unit (RPU) tailored for the execution of those Megablocks. The system is able to transparently movebcomputations from the microprocessor to the RPU at runtime. A prototype implementation of the system using a cacheless MicroBlaze microprocessor running code located in external memory reaches speedups from to for a set of 14 benchmark kernels. For a system setup which maximizes microprocessor performance by having the application code located in internal block RAMs, speedups from to were estimated.

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A Flexible Design Flow for Software IP Binding in FPGA

Cited by 22 publications

References 31 publications

A new approach for data processing in supply chain network based on FPGA

A new approach for data processing in supply chain network based on FPGA

A Pragmatic Per-Device Licensing Scheme for Hardware IP Cores on SRAM-Based FPGAs

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

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