A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic

Hafer, Lou; Parker, Alice C.

doi:10.1109/tcad.1983.1270016

Cited by 115 publications

(20 citation statements)

References 9 publications

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“…A problem which is common to several integrated scheduling and assignment approaches (Landwehr et al 1994, Hafer andParker 1983) is the fact that the number of instances of a certain component type is usually unknown before scheduling. Hence, for each component type m, a certain number of "potentially required" instance indices {krn,l' krn ,2, ... krn,u m } must be used in the IP-model.…”

Section: Figure 1 Isomorphic Rt-structuresmentioning

confidence: 99%

See 1 more Smart Citation

Exploiting Isomorphism for Speeding-Up Instance-Binding in an Integrated Scheduling, Allocation and Assignment Approach to Architectural Synthesis

Landwehr

Marwedel

Markhof

et al. 1997

Hardware Description Languages and Their Applications

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Register-Transfer (RT -) level netlists are said to be isomorphic if they can be made identical by relabeling RT-components. RT-netlists can be generated by architectural synthesis. In order to consider just the essential design decisions, architectural synthesis should consider only a single representative of sets of isomorphic netlists. In this paper, we are using netlist isomorphism for the very first time in architectural synthesis. Furthermore, we describe how an integer-programming (IP-) based synthesis technique can be extended to take advantage of netlist isomorphism.

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Section: Figure 1 Isomorphic Rt-structuresmentioning

confidence: 99%

“…One of the early approaches to architectural synthesis is the IP-model of Hafer (Hafer and Parker 1983). The model does not use any kind of normal form for labeling components and hence implicitly analyses multiple solutions which are isomorphic.…”

Section: Related Workmentioning

confidence: 99%

Exploiting Isomorphism for Speeding-Up Instance-Binding in an Integrated Scheduling, Allocation and Assignment Approach to Architectural Synthesis

Landwehr

Marwedel

Markhof

et al. 1997

Hardware Description Languages and Their Applications

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“…Since Hafer and Parker [10] rst proposed mixed ILP as the optimization method for datapath synthesis, numerous authors demonstrated the eectiveness of this method as a scheduling, assignment, and resource allocation tool. Notable work includes research reported in [6].…”

Section: Integer-linear Programmingmentioning

confidence: 99%

Optimal ILP-based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming

DeCastelo-Vide-e-Souza¹

1995

32nd Design Automation Conference

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{ System level design and behavior transformations have been rapidly establishing themselves as design steps with the most inuential impact onnal performance metrics, throughput and latency, o f a design. In this paper we develop a formal ILPbased approach for throughput and latency optimization when algorithm-architecture matching, retiming, and pipelining are considered simultaneously. The effectiveness of the approach is demonstrated on several real-life examples.

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“…Initial work to tackle this problem included the development of a mathematical model for the data path [7] to describe the conditions and relationships to be satisfied. Mixed integer-linear programming techniques were used.…”

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confidence: 99%

Algorithms for hardware allocation in data path synthesis

Devadas

Newton

1989

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

204

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Abstract-The most creative step in synthesizing data paths executing software descriptions is the hardware allocation process. New algorithms for the simultaneous costlresource constrained allocation of registers, arithmetic units, and interconnect in a data path have been developed. The entire allocation process can be formulated as a twodimensional placement problem of microinstructions in space and time. This formulation readily lends itself to the use of a variety of heuristics for solving the allocation problem. We present simulated-annealingbased algorithms which provide excellent solutions to this formulation of the allocation problem. These algorithms operate under a variety of user-specifable constraints on hardware resources and costs. They also incorporate conditional resource sharing and simultaneously address all aspects of the allocation problem, namely register, arithmetic unit and interconnect allocation, while effectively exploring the existing tradeoffs in the design space.

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A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic

Cited by 115 publications

References 9 publications

Exploiting Isomorphism for Speeding-Up Instance-Binding in an Integrated Scheduling, Allocation and Assignment Approach to Architectural Synthesis

Exploiting Isomorphism for Speeding-Up Instance-Binding in an Integrated Scheduling, Allocation and Assignment Approach to Architectural Synthesis

Optimal ILP-based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming

Algorithms for hardware allocation in data path synthesis

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