A Fully Integrated Reprogrammable CMOS-RRAM Compute-in-Memory Coprocessor for Neuromorphic Applications

Correll, Justin M.; Bothra, Vishishtha; Cai, Fuxi; Lim, Yong; Lee, Seung Hwan; Lee, Seungjong; Lü, Wei; Zhang, Zhengya; Flynn, Michael P.

doi:10.1109/jxcdc.2020.2992228

Cited by 24 publications

(11 citation statements)

References 14 publications

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“…This design rule is especially important for unconventional memristors such as those made from transition metal dichalcogenides 5 and organic materials 48 that typically have poor retention. Phase separation also provides an avenue to improve retention in non-filamentary interfacial memristors 49 and electrochemical random access memory 50 (ECRAM), which has more reliable switching but poorer retention.…”

Section: Discussionmentioning

confidence: 99%

Thermodynamic origin of nonvolatility in resistive switching

Appachar

et al. 2022

Preprint

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Electronic switches based on the migration of high-density point defects, or memristors, are poised to revolutionize post-digital electronics. Despite significant research, key mechanisms for filament formation and oxygen transport remain unresolved, thus hindering our ability to predict and design crucial device properties. For example, predicted retention times based on current models can be 10 orders of magnitude lower than ones experimentally realized. Here, using electrical measurements, chemical spectroscopy, and first-principles calculations on tantalum oxide memristors, we reveal that the formation and stability of conductive filaments crucially depend on the stability of the amorphous oxygen-rich and oxygen-poor compounds, which undergo composition phase separation. Including the previously neglected effects of this amorphous phase separation reconciles unexplained discrepancies and enables predictive design of key performance indicators such as retention stability. This result emphasizes non-ideal thermodynamic interactions as key design criteria in post-digital devices with defect densities substantially exceeding those of today’s covalent semiconductors.

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Section: Discussionmentioning

confidence: 99%

Thermodynamic origin of nonvolatility in resistive switching

Appachar

et al. 2022

Preprint

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“…Fig. 11 illustrates the architecture of a fully integrated reprogrammable ReRAM coprocessor for MAC [46]. It consists of a reduced instruction set computer (RISC) processor, multiple SRAMs, a memory controller, and a ReRAM PIM macro with the mixed-signal interface.…”

Section: F New Directions For Reram Pim Research 1) Rerammentioning

confidence: 99%

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning

Kim

Xie

Chen

et al. 2022

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Artificial intelligence (AI) and machine learning (ML) are revolutionizing many fields of study, such as visual recognition, natural language processing, autonomous vehicles, and prediction. Traditional von-Neumann computing architecture with separated processing elements and memory devices have been improving their computing performances rapidly with the scaling of process technology. However, in the era of AI and ML, data transfer between memory devices and processing elements becomes the bottleneck of the system. To address this data movement issue, memory-centric computing takes an approach of merging the memory devices with processing elements so that computations can be done in the same location without moving any data. Processing-In-Memory (PIM) has attracted research community's attention because it can improve the energy efficiency of memory-centric computing systems substantially by minimizing the data movement. Even though the benefits of PIM are well accepted, its limitations and challenges have not been investigated thoroughly. This paper presents a comprehensive investigation of state-of-the-art PIM research works based on various memory device types, such as static-random-access-memory (SRAM), dynamic-random-access-memory (DRAM), and resistive memory (ReRAM). We will present the overview of PIM designs in each memory type, covering from bit cells, circuits, and architecture. Then, a new software stack standard and its challenges for incorporating PIM with the conventional computing architecture will be discussed. Finally, we will discuss various future research directions in PIM for further reducing the data conversion overhead, improving test accuracy, and minimizing intra-memory data movement.

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“…In a follow up research, Correll et al [96] studied the semantics and architectures for the analog design of a CMOS-RRAM reprogrammable neuromorphic chip. By employing RRAM, the bottleneck for data availability in data hungry applications, including AI and machine learning applications, can be bypassed.…”

Section: Cmos-rram Architecturementioning

confidence: 99%

“…CNNs architecture [87] Multiplication function design [92] Memristive FPGA emulator [93] Controller-based network [91] Finite time synchronization in RNN [88] Multi-layer circuit design [89] DNN activation circuits [90] DNN for RRAM [94][95] CMOS-RRAM Neuromorphic arch. [96]…”

Section: Memristive Neural Networkmentioning

confidence: 99%

On Memristors for Enabling Energy Efficient and Enhanced Cognitive Network Functions

Saleh

Koldehofe

2022

IEEE Access

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The high performance requirements of nowadays computer networks are limiting their ability to support important requirements of the future. Two important properties essential in assuring cost-efficient computer networks and supporting new challenging network scenarios are operating energy efficient and supporting cognitive computational models. These requirements are hard to fulfill without challenging the current architecture behind network packet processing elements such as routers and switches. Notably, these are currently dominated by the use of traditional transistor-based components. In this article, we contribute with an in-depth analysis of alternative architectural design decisions to improve the energy footprint and computational capabilities of future network packet processors by shifting from transistor-based components to a novel component named Memristor. A memristor is a computational component characterized by non-volatile operations on a physical state, mostly represented in form of (electrical) resistance. Its state can be read or altered by input signals, e.g. electrical pulses, where the future state always depends on the past state. Unlike in traditional von Neumann architectures, the principles behind memristors impose that memory operations and computations are inherently colocated. In combination with the non-volatility, this allows to build memristors at nanoscale size and significantly reduce the energy consumption. At the same time, memristors appear to be highly suitable to model cognitive functionality due to the state dependence transitions in the memristor. In cognitive architectures, our survey contributes to the study of memristorbased Ternary Content Addressable Memory (TCAM) used for storage of cognitive rules inside packet processors. Moreover, we analyze the memristor-based novel cognitive computational architectures built upon self-learning capabilities by harnessing from non-volatility and state-based response of memristors (including reconfigurable architectures, reservoir computation architectures, neural network architectures and neuromorphic computing architectures).

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A Fully Integrated Reprogrammable CMOS-RRAM Compute-in-Memory Coprocessor for Neuromorphic Applications

Cited by 24 publications

References 14 publications

Thermodynamic origin of nonvolatility in resistive switching

Thermodynamic origin of nonvolatility in resistive switching

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning

On Memristors for Enabling Energy Efficient and Enhanced Cognitive Network Functions

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