2017
DOI: 10.1109/tpel.2016.2556939
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A Fully Integrated Watt-Level Power Transfer System With On-Chip Galvanic Isolation in Silicon Technology

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Cited by 26 publications
(29 citation statements)
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“…Moreover, the higher switching frequencies allowed by wideband power devices, such as gallium nitride high-electron-mobility transistors (GaN HEMT) and silicon carbide (SiC) MOSFETs, will require a CMTI beyond 200 kV/µs [2,3]. Traditional chip-scale isolators are based on capacitors [4,5], transformers [6][7][8][9][10][11][12][13][14], and LC hybrid networks [15], which exploit either thick silicon dioxide or polyimide layers as an isolation barrier. These approaches reveal inherent limitations in terms of both isolation rating and CMTI due to the maximum manufacturable dielectric thickness and related capacitive parasitics, respectively.…”
Section: Galvanic Isolators Based On Rf Planar Couplingmentioning
confidence: 99%
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“…Moreover, the higher switching frequencies allowed by wideband power devices, such as gallium nitride high-electron-mobility transistors (GaN HEMT) and silicon carbide (SiC) MOSFETs, will require a CMTI beyond 200 kV/µs [2,3]. Traditional chip-scale isolators are based on capacitors [4,5], transformers [6][7][8][9][10][11][12][13][14], and LC hybrid networks [15], which exploit either thick silicon dioxide or polyimide layers as an isolation barrier. These approaches reveal inherent limitations in terms of both isolation rating and CMTI due to the maximum manufacturable dielectric thickness and related capacitive parasitics, respectively.…”
Section: Galvanic Isolators Based On Rf Planar Couplingmentioning
confidence: 99%
“…Oxide and polyimide galvanic barriers have different breakdown voltage (BV), fabrication costs, and especially integration levels. Indeed, an oxide barrier can be integrated along with the active circuitry in a two-chip system-inpackage (SiP) for each isolated channel (see Figure 2a), guaranteeing an isolation rating of about 6 kV thanks to the high SiO 2 BV (i.e., about 1000 V/µm) [6,19]. However, oxide insulation is upper limited by the maximum reliable thickness (i.e., about 10 µm) due to both wafer mechanical stress and second-order BV effects.…”
Section: Chip-scale Isolation Vs Package-scale Isolationmentioning
confidence: 99%
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“…A number of CMLIs topologies utilizing half-bridge and H-bridge modules have been implemented for Fig. 1 The proposed three-phase CMLI with two half-bridge cells per phase leg high voltage applications and can be found in the literatures [19,31]. The rating of the switching devices in the proposed CMLI can be identified according to the voltage requirement of the intended application.…”
Section: The Proposed Multilevel Inverter and Its Modulation Strategymentioning
confidence: 99%
“…The rating of the switching devices in the proposed CMLI can be identified according to the voltage requirement of the intended application. It is worth mentioning that as the threephase transformer is an essential component in the proposed topology, it will inherently fulfill the galvanic isolation requirement for renewable energy grid-connected applications [31]. The main focus of this paper is to develop a new inverter topology.…”
Section: The Proposed Multilevel Inverter and Its Modulation Strategymentioning
confidence: 99%