A hardware sharing architecture of deblocking filter for VP8 and H.264/AVC video coding

Chou, Yu-Lin; Wu, Chung-Bin

doi:10.1109/iscas.2012.6271647

Cited by 4 publications

(2 citation statements)

References 6 publications

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“…The VP8 format [4], for instance, defines normal and simple filtering which include a rather similar computation in comparison to the H264 [5] filtering modes. In fact, the similarities are so close to each other that the same hardware can be designed to support both of these deblocking filters [6]. The challenge in many video standards is their fine grained control how the blocks are processed.…”

Section: Deblocking Filtermentioning

confidence: 99%

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Programmable in-loop deblock filter processor for video decoders

Janhunen

Jääskeläinen

Hannuksela

et al. 2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

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The short time to market cycle and the target to reduce design and verification costs are driving forces to design programmable implementations of the video processing algorithms. We present two processor architectures the first one representing an application-specific instruction set processor (ASIP) design, whereas the second architecture represents a domain-specific instruction-set processor (DSIP) architecture with more general purpose instruction-set. In this work, we present results for H264 and VP8 in-loop deblocking algorithms. The processors are based on the transport triggered architecture which provides scalable instruction-level parallelism and, thanks to its simple structure, lend itself to cost effective designs. Both of the designs are programmed with C language with a minimal additional parallelism markup. The designs fulfill realtime requirements for filtering macroblocks in high-definition video. The first architecture, based on special function units, filters a high-definition stream (1920 × 1080) at 75 fps, whereas the second architecture, which provides a better programmability, filters the stream at 53 fps. The processors run on 200 MHz clock frequency and the areas vary from 146k to 373k gate equivalents depending on the processor architecture.

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Section: Deblocking Filtermentioning

confidence: 99%

“…The challenge in many video standards is their fine grained control how the blocks are processed. The deblock filtering in H264 and VP8 standards is a good example having a fine grained control for edge filtering [6] leading to conditional execution making an efficient resource allocation harder.…”

Section: Deblocking Filtermentioning

confidence: 99%