A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion

Design Concepts for a Virtualizable Embedded MPSoC Architecture

“…The work of [Huang 2009] virtualizes hardware components in HW-SW designs. Another approach targets the virtualization of whole FPGAs [Figuli 2011, Sidiropoulos 2013. Task switching procedures for hardware tasks were proposed, e. g., in , Jozwik 2012, with the last one explicitly targeting virtualization features.…”

A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization

“…Leading predefined patterns in the bitstreams control bypassing mechanisms in the configuration units, thus we can achieve a fine grain partial reconfiguration at slice level. More details about the architecture of the V-FPGA and the reconfiguration mechanisms can be found in [7] and [8].…”

“…However, having a set of differently sized applications to be mapped, this is not the most efficient way because for small applications there might be lots of CLBs on the allocated core unutilized (wasted). That is why our architecture supports with "CoreFusion" [8], a method that allows to merge adjacent cores on their boundaries to one bigger core when needed. CoreFusion when used with many small/medium cores rather than few big cores provides a higher flexibility to resource allocation and improves the overall utilization and the number of applications that can be run concurrently.…”

On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation

“…Previous works proved the efficiency of such an architecture at implementing different application domains described in a hardware description language (e.g. VHDL or Verilog) [2] [3]. Apart from these virtual FPGA cores, the target architecture includes also a microprocessor, a configuration controller, an external memory and AMBA busses for onchip communication and configuration.…”