A high‐order curvature‐corrected CMOS bandgap voltage reference with constant current technique

Abstract

SUMMARY A high‐order curvature‐corrected complementary metal–oxide–semiconductor (CMOS) bandgap voltage reference (BGR), utilizing the temperature‐dependent resistor and constant current technique, is presented. Considering the process variation, a resistor trimming network is introduced in this work. The circuit is implemented in a standard 0.35‐µm CMOS process. The measurement results have confirmed that the proposed BGR operates with a supply voltage of 1.8 V, consuming 45 μW at room temperature (25 °C), and the temperature coefficient of the output voltage reference is about 5.5 ppm/°C from −40 °C to 125 °C. The measured power supply rejection ratio is −38.8 dB at 1 kHz. The BGR is compatible with low‐voltage and low‐power circuit design when the structure of operational amplifiers and all the devices in the proposed bandgap reference are properly designed. Copyright © 2012 John Wiley & Sons, Ltd.

Low temperature coefficient and low line sensitivity subthreshold curvature‐compensated voltage reference

“…The voltages V PTAT and V CTAT are generally obtained by voltage drops of either forward‐biased PN junction diode, 11–13 base‐emitter junction voltages of the BJTs, 14–29 or gate‐to‐source voltages of subthreshold MOS transistors 30–43 . The first‐order temperature‐compensated voltage reference circuits have been reported in the literature, which are formed by using diodes, BJTs, MOS transistors, or by combination of these devices 11,12,14–17,26,28–41 . The voltage reference circuit presented by Banba et al 11 uses diodes, resistors, and operational amplifier.…”

“…The voltage reference reported by Cucchi et al 17 uses BJTs, which results in high‐power consumption and increased chip area. In various voltage reference circuits, the operational amplifiers are used to increase the accuracy, but it makes the design more complicated along with high supply voltage requirement, high‐power consumption, and chip area 26,28–30 . Leung et al 31 proposed a voltage reference based on weighted difference of gate‐to‐source voltages of NMOS and PMOS transistors working in the saturation region.…”

A 0.7 V, 2.7 μW, 12.9 ppm/° C over 180° C CMOS subthreshold voltage reference

“…These designs are limited by the base‐emitter non‐linearities at a TC of around 20 ppm/°C, over a temperature range of 100°C. Alternative proposed topologies provide high‐order curvature compensation by cancelling part of the nonlinear dependence of the bipolar junction transistor (BJT) base‐emitter voltage, although they require complex structures with a high power consumption and large area. More recent topologies use the temperature‐dependent threshold voltage of a MOSFET and carrier mobility, to generate a PTAT voltage/current and a complementary to absolute temperature (CTAT) voltage/current, which are summed in order to provide a first‐order compensated voltage .…”

A 0.75‐V, 4‐μW, 15‐ppm/°C, 190 °C temperature range, voltage reference

“…The accuracy of this method is limited by the non-linearities of the bipolar junction transistor. In order to deal with this issue, some designs utilize a curvature temperature compensation method, thus achieving improved temperature drift (TD) performance [6][7][8][9][10][11][12][13][14][15][16][17][18]. Subsequent architectures focus on using only MOS devices to generate a reference voltage [19][20][21][22][23][24][25][26].…”