A high performance 0.25 mu m CMOS technology

Davari, B.; Chang, Wen-Hao; Wordeman, M.R.; Oh, Chulmin; Taur, Yuan; Petrillo, Karen; Moy, D.; Bucchignano, J.; Ng, H.; Rosenfield, M. G.; Hohn, Fritz J.; Rodríguez, Manuel de León

doi:10.1109/iedm.1988.32749

Cited by 23 publications

(12 citation statements)

References 3 publications

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“…As shown in Fig. 1(b), the gate delay is increased by 22% when the Vdd is reduced from 3.3 to 2.5 V. In addition, at low , the threshold voltage must be lowered in order to maintain high current drive, which results in high off-stage leakage [1], [2]. In this letter, we show that As-only junctions limit the performance due to low hot carrier life time.…”

Section: Introductionmentioning

confidence: 90%

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A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology

Nayak

Hao

Umali

et al. 1997

IEEE Electron Device Lett.

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A comprehensive study of P, As, and hybrid As/P nLDD junctions is presented in terms of performance, reliability, and manufacturability for the first time. It is found that As junctions limit the performance of deep submicron devices due to unacceptable hot-carrier reliability, whereas a hybrid junction (light dose P added to medium dose As) dramatically improves hot-carrier reliability while maintaining high performance and manufacturability. For L e of 0.19 m, using this hybrid junction in a manufacturing process, an inverter gate delay of 32 ps, dc hot carrier life time exceeding ten years, and off-state leakage below 30 pA/m at 2.9 V have been achieved.

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Section: Introductionmentioning

confidence: 90%

“…Using As-only n , high-performance CMOS logic technology operating at 2.5 V has been reported [1]- [3]. Due to the sharp As junction, the power supply voltage must be reduced below 2.5 V in order to maintain sufficient hot carrier reliability margin.…”

Section: Introductionmentioning

confidence: 99%

A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology

Nayak

Hao

Umali

et al. 1997

IEEE Electron Device Lett.

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“…This necessitates the use of a p' doped gate electrode for the PMOS transistors, which is typically accomplished with boron. Boron penetration into the oxide or the channel is therefore a major concern for deep sub-micron CMOS technology [1,2] particularly with the thermal budgets and ultra-thin gate dielectrics required in today's CMOS processes. The addition of fluorine, introduced by implantation with BF 2 , or exposure to hydrogen containing ambients is shown to accelerate the rate of boron diffusion through thin gate dielectrics [3,4,5].…”

Section: Introductionmentioning

confidence: 99%

Nitric Oxide Rapid Thermal Nitridation of Thin Gate Oxides

et al. 1997

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Nitric oxide rapid thermal nitridation of thin gate oxides was investigated. Oxides from 25 to 55 A were grown in 02 and subsequently nitrided in a nitric oxide (NO) ambient using an Applied Materials RTP Centura chamber. Nitrogen incorporation and film thickness growth during NO nitridation were evaluated. Peak nitrogen incorporation was most strongly influenced by temperature and time, with moderate influence by initial oxide thickness, and no significant influence due to NO flow rate. Peak nitrogen concentrations ranged from 1 to 9 atomic percent as characterized by Secondary Ion Mass Spectrometry (SIMS) analysis. Oxide growth during nitridation ranged from 2 A to II A with no degradation in uniformity. These data were used in the design of two 40 A oxynitride processes incorporating 2 and 4 peak atomic percent nitrogen. High quality MOS capacitors were demonstrated with these dielectrics. Performance was compared against a baseline furnace process as well as non-nitrided RTO. Throughout this work, the chamber integrity was monitored using visual inspection, minority carrier lifetime (MCLT) and surface photovoltage (SPV). No contamination, corrosion or other degradation of the process chamber was observed in over 6 months' operation with over 700 NO processes completed. The controllability, uniformity and high nitrogen incorporation of rapid thermal NO nitridation make it an attractive process for deep sub-micron gate insulators.

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“…4 shows gate delays versus power supply voltage for both high V, and low V, devices. For the low V, device, the delay is 24 ps/stage at Vu= 1.5V, which is 2X faster than 0.25 pm CMOS [2]. At lower voltages, the delay increases, but is stdl faster than 0.25pm CMOS even below 1 V. At 0.5 V power supply, the delay is 106 ps/stage, as shown by the waveform in …”

Section: Device Resultsmentioning

confidence: 92%

“…2, where constant delay, active power, and standby power contours are plotted in a threshold voltage-power supply design plane. Both the delay and power are normalized to a reference set by 2.5 V, 0.25 pm CMOS devices [2]. In general, the active power increases towards the right roughly as Qd, while the standby power increases exponentially downward as exp( -qV,/kT).…”

Section: Desigx Considerationmentioning

confidence: 99%

An ultra-low power 0.1 μm CMOS

Mii

Wind

Taur

et al.

Proceedings of 1994 VLSI Technology Symposium

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Ultra-low power operation of O.lpm CMOS is demonstrated at power supply voltages well below 1 V. Design trade-offs among gate delay, active power, and standby power are canied out in a power supplythreshold voltage design space. Experimental results show a ring o s d a t o r delay of 106 ps at a power supply voltage of 0.5 V, and a minimum power-delay product of 0.03 fJ/stage (switching factor = 0.01) at 0.4 V. A 20X reduction in powerlcircuit is achieved at the same performance level as 0.25pm CMOS.

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A high performance 0.25 mu m CMOS technology

Cited by 23 publications

References 3 publications

A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology

A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology

Nitric Oxide Rapid Thermal Nitridation of Thin Gate Oxides

An ultra-low power 0.1 μm CMOS

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