A high-performance analog front-end 14-bit codec for 2.7-V digital cellular phones

Nicollini, G.; Pernici, S.; Confalonieri, P.; Crippa, C.; Nagari, Angelo; Mariani, S.; Moioli, Matteo; Dallavalle, C.

doi:10.1109/4.705354

Cited by 12 publications

(4 citation statements)

References 10 publications

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“…Fig. 19 shows the proposed SAR ADC block diagram based on the topology in [40], in which the building blocks constitute a track-and-hold (T/H) circuit, DAC, comparator, and a 10-bit SAR controller. In this charge redistributionbased architecture, the capacitors in the main DAC serve as the sampling capacitor for T/H.…”

Section: A Adc Architecturementioning

confidence: 99%

Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity

Wang

Dehollain

2015

IEEE Sensors J.

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This paper presents the design and implementation of a 46-kS/s CMOS switch-capacitor dual-mode capacitive sensor interface circuit for inkjet-printed capacitive humidity sensors. The specifications of the interface circuit, which includes a capacitance-to-voltage (C2V) converter combined with an analog-to-digital converter (ADC), are optimized at system level, emphasizing the C2V operation followed by the data converter. A closed form of the maximum output range of a single-stage C2V is provided to prevent cascade amplification. The gain-boosting technique is utilized in the operational transconductance amplifier design to improve the closed-loop linearity. The correlated double sampling technique attenuates the dc offset and low-frequency flicker noise from C2V. A 10-b successive approximation register ADC digitizes the output of C2V. The total area of the digital-to-analog (DAC) array is limited not only by the matching behavior, but also by the noise performance of C2V. The rail-to-rail ability is required to render the compatibility with various possible sensor inputs. A single-ended cascaded binary-weighted capacitive DAC is used to implement the charge redistribution binary search algorithm. The circuit is implemented in a 0.18-µm CMOS technology and occupies an area of 1.2 mm 2 . The tested prototype shows 0.69% nonlinearity in mode 1 and 1.38% nonlinearity in mode 2. The SNR of mode 1 is 50.1 dB and that of mode 2 is 36.5 dB, which meets the specification of 7.32 b in mode 1 and 5.32 b in mode 2. The total power consumption of the capacitive sensor interface is 70 µW.Index Terms-Capacitive sensor interface, C2V, SAR ADC, CDS, opamp, noise optimization, power-efficient system.

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Section: A Adc Architecturementioning

confidence: 99%

Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity

Wang

Dehollain

2015

IEEE Sensors J.

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“…Since the actual value of the capacitance ratio is not exactly known it is approximated by its nominal value. This can be modeled by an additive error as well: (10) Then the digital output can be rewritten as ADC (11) This equation indicates the main properties of the extended counting conversion technique. The first and most important property is that both errors and are divided by , the number of counting steps.…”

Section: A Principlementioning

confidence: 99%

“…However, the linearity depends on component matching and therefore high resolution is difficult to achieve [6]. Recently, a circuit has been presented where through a combination of careful layout and process control up to 14-b component matching was demonstrated [10]. However, such a high accuracy is very difficult to achieve in most standard CMOS processes.…”

Section: Introductionmentioning

confidence: 99%

A 13.5-b 1.2-V micropower extended counting A/D converter

Rombouts

Wilde

Weyten

2001

IEEE J. Solid-State Circuits

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This work presents a study of the extended counting technique for a 1.2-V micropower voice-band A/D converter. This extended counting technique is a blend of 61 modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. To achieve this, the converter successively operates first as a first-order 61 modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. An experimental prototype was designed in 0.8-m CMOS. With a 1.2-V power supply, it consumes 150 W of power at a 16-kHz Nyquist sampling frequency. The measured peak S (N + THD) was 80 dB and the dynamic range 82 dB. The converter core including the controller and all reconstruction logic occupies about 1 3 1 mm 2 of chip area. This is considerably less than a complete 61 modulation A/D converter where the digital decimation filter would occupy a significant amount of chip area.

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“…Capacitor arrays are widely used for DAC and Successive Approximation ADC designs [1]- [3]. The use of a binary-weighted capacitor (BWC) array was first reported in 1975 [4].…”

Section: Introductionmentioning

confidence: 99%

Pseudo C-2C ladder-based data converter technique

Liang

2001

IEEE Trans. Circuits Syst. II

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A C-2C ladder-based DAC architecture is potentially very attractive because of its small area, high speed and low power consumption. However, the parasitic capacitances on the interconnecting nodes of a C-2C ladder significantly deteriorate the linearity of the DAC and restrict its application. In this paper, a pseudo C-2C ladder structure is proposed. It maintains the advantages of conventional C-2C ladders and effectively compensates for the parasitic effects by adjusting the capacitor ratio in a C-2 C ladder. As a result, high linearity may be achieved in standard CMOS technologies. The technique is illustrated with the design of a 12-bit CMOS DAC.Index Terms-Analog-to-digital converters (ADC), CMOS data converters, differential nonlinearity (DNL), digital-to-analog converters (DAC), integral nonlinearity (INL), pseudo C-2C ladder.

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A high-performance analog front-end 14-bit codec for 2.7-V digital cellular phones

Cited by 12 publications

References 10 publications

Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity

Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity

A 13.5-b 1.2-V micropower extended counting A/D converter

Pseudo C-2C ladder-based data converter technique

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