A high performance and low energy intra prediction hardware for High Efficiency Video Coding

Kalalı, Ercan; Adibelli, Yusuf; Hamzaoğlu, İlker

doi:10.1109/fpl.2012.6339161

Cited by 54 publications

(36 citation statements)

References 2 publications

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“…The proposed FPGA implementation consumes less power than the one proposed in [8]. Since the HEVC intra prediction hardware proposed in [13] performs intra prediction only for 4x4 and 8x8 PU sizes, it has smaller area and consumes less power than the one proposed in this paper.…”

Section: Proposed Hevc Intra Prediction Hardwarementioning

confidence: 94%

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An efficient FPGA implementation of HEVC intra prediction

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Mert

Kalalı

et al. 2018

2018 IEEE International Conference on Consumer Electronics (ICCE)

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Abstract-Intra prediction algorithm used in High EfficiencyVideo Coding (HEVC) standard has very high computational complexity. In this paper, an efficient FPGA implementation of HEVC intra prediction is proposed for 4x4, 8x8, 16x16 and 32x32 angular prediction modes. In the proposed FPGA implementation, one intra angular prediction equation is implemented using one DSP block in FPGA. The proposed FPGA implementation, in the worst case, can process 55 Full HD (1920x1080) video frames per second. It has up to 34.66% less energy consumption than the original FPGA implementation of HEVC intra prediction. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.

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Section: Proposed Hevc Intra Prediction Hardwarementioning

confidence: 94%

“…Several HEVC intra prediction hardware are proposed in the literature [8]- [13]. In section III, they are compared with the HEVC intra prediction hardware proposed in this paper.…”

Section: Introductionmentioning

confidence: 99%

An efficient FPGA implementation of HEVC intra prediction

Azgın

Mert

Kalalı

et al. 2018

2018 IEEE International Conference on Consumer Electronics (ICCE)

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“…These three FIR filters type A, type B and type C are shown in (1), (2), and (3), respectively. The shift1 value is determined based on bit depth of the pixel.…”

Section: Hevc Fractional Interpolation Algorithmmentioning

confidence: 99%

An HEVC fractional interpolation hardware using memory based constant multiplication

Mert¹,

Kalalı²,

Hamzaoğlu³

2018

2018 IEEE International Conference on Consumer Electronics (ICCE)

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Abstract-Fractional interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. In this paper, an HEVC fractional interpolation hardware using memory based constant multiplication is proposed. The proposed hardware uses memory based constant multiplication technique for implementing multiplication with constant coefficients. The proposed memory based constant multiplication hardware stores pre-computed products of an input pixel with multiple constant coefficients in memory. Several optimizations are proposed to reduce memory size. The proposed HEVC fractional interpolation hardware, in the worst case, can process 35 quad full HD (3840x2160) video frames per second. It has up to 31% less energy consumption than original HEVC fractional interpolation hardware.

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“…There are a few HEVC intra prediction hardware implementations in the literature [16], [17]. Since these hardware only implement HEVC intra prediction, the HEVC intra mode decision hardware proposed in this paper cannot be compared with them.…”

Section: Fig 1 Addition Amounts In Hevc and H264 Satd Calculationsmentioning

confidence: 99%