A high performance CMOS chipset for FFT processors

Calculating the FHT in hardware

“…The CUSP dedicated-FFT processor [LIND85] has a very simple host interface and an elegant solution to controlling the overflow associated with fixed-point arithmetic. But the decision to implement bit-serial multipliers results in a single-processor system that is easily outperformed by ours and others [SHEN88,BURS88].…”

“…One of the most successful commercial efforts in this area is Honeywell's HDSP66110/220 chip-set [SHEN88]. Capable of performing a 1024-point real-valued transform in 63 microseconds, this product combines a number of multiprocessing techniques to implement the fastest single-processor, radix-4 FFT engine known to the author.…”

COBRA: a 100-MOPS single-chip programmable and expandable FFT

“…The first problem is memory access conflicts during processing because the data output from one cascaded stage should be reordered before being passed to the next cascaded stage. To solve this problem, several methods such as phase rotation [11], commutation [15], and special memory structures [6] have been introduced. The memory access conflict problem can be minimized using these methods at the cost of extra hardware or extra delay in the data path.…”

“…To implement a 1024-point radix-4 FFT system, 256 butterfly processors are required. Taking the state-of-the-art DASP/PAC chipset [6] from Array MicroSystems Inc. as an example, which has an area of about 2.4 cm using 1.2-m CMOS technology, about 61 cm of silicon area is required. Even with WSI technology, only short transform-length FFT's can be implemented using bit-parallel arithmetic units.…”