A High-Performance Gate Engineered InGaN Dopingless Tunnel FET

Duan, Xiaoling; Zhang, Jincheng; Wang, Shulong; Li, Yao; Xu, Shengrui; Hao, Yue

doi:10.1109/ted.2018.2796848

Cited by 78 publications

(53 citation statements)

References 27 publications

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“…The boundary conditions set for region R1 considers band‐to‐band tunnelling, where the same is not regarded in R2. The dual‐metal DG TFET structure that exhibits high dc performance has been proposed earlier [18, 19]. To get accuracy, our simulation result is calibrated with the reported data for dual‐metal DG TFET [18].…”

Section: Resultsmentioning

confidence: 99%

Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

Bose

Roy

2020

IET Circuits, Devices & Systems

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Section: Resultsmentioning

confidence: 99%

Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

Bose

Roy

2020

IET Circuits, Devices & Systems

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“…For simplicity, we have not included trap-assisted tunneling in our simulations. However, it should be noted that trap-assisted tunneling can increase SS avg or I OFF [29], [30]. It is important to point out that the focus of this work is to demonstrate the relative improvement in electrical characteristics of the AND logic realized using an HJ-TFET compared to an Si-TFET, rather than reporting the exact current values in these devices.…”

Section: And and Nand Logic Function Using Si/ge Heterojunction Dmentioning

confidence: 98%

Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis

Garg

Saurabh

2019

IEEE Access

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Recently, a compact realization of logic gates using double-gate tunnel field effect transistors (DGTFETs) with independently-controlled gate has been proposed. The key elements in the proposed implementation are the suppression of the tunneling at the surface using gate-source overlap and enable tunneling inside the TFET body by choosing appropriate silicon body thickness. Though these implementations are compact, our study reveals that there are a few critical problems: high average subthreshold swing (SS avg), low ON-state current (I ON) and large propagation delay (t pd). In this paper, we examine the root cause of these problems and explore solutions to tackle them. It is demonstrated that the techniques that boost the I ON in a TFET do not necessarily increase the I ON /I OFF ratio in the proposed implementations. The efficacy of these techniques in improving the I ON /I OFF ratio depends on whether the gate-source overlap is able to suppress the tunneling at the surface and restrict the OFF-state current (I OFF). Furthermore, it is demonstrated that, for the AND functionality, compared to a purely silicon-based DGTFET (Si-TFET) employing silicongermanium heterojunction DGTFET (HJ-TFET) results in an increase in the I ON by 143×, an increase in the I ON /I OFF ratio by two orders of magnitude and an improvement in the SS avg by 45%, at V DD = 0.6 V. Moreover, a compact NAND gate realized using the proposed HJ-TFETs exhibits two orders of magnitude lower t pd , compared to the NAND gate realized using Si-TFET.

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“…Moreover, as the TFET is adopted because of its potential as an ultra-low power device, and power dissipation is minimized by scaling supply voltage.The base silicon [18] Si DL-TFET gives better SS in comparison to [22] at lowersupply voltage. Therefore, the authors in this paper have reproduced the results ofbasic structure [18] i.e. Si-DLTFET for further device performance improvement.Here, considering the base device structure Si-DLTFET of [18] in the presentmanuscript, the optimization of dielectric thickness under both source and gateelectrodes has been carried out here.…”

Section: Introductionmentioning

confidence: 99%

Ultra Steep Ge-source Dopingless Tunnelling Field Effect Transistor with Enhanced Drive Current

Priyadarshani

Singh

2021

Preprint

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Ge-source dopingless tunnelling field effect transistor (Ge-source DLTFET) with the optimization of dielectric oxide thickness under the source and the gate contacts is proposed and investigated by calibrated 2D TCAD device simulation. As the structure is realized using dopingless technique, this enables lower thermal budget, higher immunity towards the random dopant fluctuations (RDFs) effects and velocity degradation effects. The optimization of dielectric thickness has been done to tune the carrier concentrations induced in source and channel regions in order to improve the device performance. The drive current is magnificently enhanced along with ION/IOFF ratio, peak transconductance and ultra-steep subthreshold slope (SS) is reported for the optimized Si-DLTFET. In addition to this by deploying Ge-source instead of Si source in optimized Si-DLTFET increases ON current slightly and OFF current gets reduced by the order of two as compared to the optimized Si-DLTFET. This improves the ION/IOFF ratio,the reported drive current for Ge-source DLTFET is 5.1×10− 4 A/µm, along with ION/IOFF ratio as 1.54×1013, peak transconductance as 1.26 mS/µm and ultra-steep SS as 1.69 mV/decade. Further, the analog, RF and linearity performance parameters have also been investigated for both the structures and demonstrated notable improvement. The energy efficiency investigationreveals a significant reduction in energy-delay product. This paper indicates thepotentials of optimized Si-DLTFET and Ge-source DLTFET as promising candidates for low power analog and RF applications and Ge-source DLTFET hasbetter device dc performance.

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A High-Performance Gate Engineered InGaN Dopingless Tunnel FET

Cited by 78 publications

References 27 publications

Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis

Ultra Steep Ge-source Dopingless Tunnelling Field Effect Transistor with Enhanced Drive Current

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