A high-performance microarchitecture with hardware-programmable functional units

Razdan, Rahul; Smith, Michael D.

doi:10.1145/192724.192749

Cited by 230 publications

(98 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…PRISC [9] is the first to explore the feasibility of a RFU on the datapath of a MIPS processor. All custom instructions must fit within a two-input/one-output signature, read and write the register file, and take a single processor cycle to execute.…”

Section: Related Workmentioning

confidence: 99%

Factors Influencing the Performance of a CPU-RFU Hybrid Architecture

Venkataramani

Sudhir

Budiu

et al. 2002

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. Closely coupling a reconfigurable fabric with a conventional processor has been shown to successfully improve the system performance. However, today's superscalar processors are both complex and adept at extracting Instruction Level Parallelism (ILP), which introduces many complex issues to the design of a hybrid CPU-RFU system. This paper examines the design of a superscalar processor augmented with a closely-coupled reconfigurable fabric. It identifies architectural and compiler issues that affect the performance of the overall system. Previous efforts at combining a processor core with a reconfigurable fabric are examined in the light of these issues. We also present simulation results that emphasize the impact of these factors.

show abstract

Section: Related Workmentioning

confidence: 99%

Factors Influencing the Performance of a CPU-RFU Hybrid Architecture

Venkataramani

Sudhir

Budiu

et al. 2002

Lecture Notes in Computer Science

View full text Add to dashboard Cite

show abstract

“…Other notable reconfigurable computing projects include the Programmable Reduced Instruction Set Computer (prisc) [21,22], garp [16], disc [31], rapid [13], the CMU Cached Virtual Hardware (cvh), PipeRench [5], and Chimaera [14,15].…”

Section: Previous Workmentioning

confidence: 99%

Compiler Optimizations for Adaptive EPIC Processors

2001

View full text Add to dashboard Cite

Abstract. Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting ways in which this silicon may be used is to leave portions of it uncommitted and re-programmable depending on an applications needs. In an earlier paper, we proposed a machine architecture for achieving this reconfigurability and compilation issues that such an architecture will face. In this paper, we will elaborate on the compiler optimization issues involved. In particular, we will outline a framework for code partitioning, instruction synthesis, configuration selection, resource allocation, and instruction scheduling. Partitioning is the problem of identifying code sections that may benefit by mapping them on to the programmable logic resources. The instruction synthesis phase generates suitable implementations for the candidates partitions and updates the machine description database with the new instructions. Configuration selection is the problem of narrowing down the choices of which synthesized instruction (from the set generated by the instruction synthesis phase) to use for each of the code regions that will be mapped to programmable logic. Unlike traditional optimizing compilers, the adaptive EPIC compiler must deal with the existence of synthesized instructions. Compilation techniques addressing each of these problems will be presented.

show abstract

“…A wider discussion of related work can be found in [2]. The PRISC [6] architecture proposed having a Reduced Instruction Set Computing (RISC) processor augmented with multiple reconfigurable function units, though the authors only produced results for an implementation with a single reconfigurable unit. These function units are stateless, which avoids additional context switch overheads.…”

Section: Related Workmentioning

confidence: 99%

Initial Analysis of the Proteus Architecture

Dales

2001

Field-Programmable Logic and Applications

View full text Add to dashboard Cite

Abstract. The Proteus Architecture proposed a general purpose microprocessor with reconfigurable function units. The ProteanARM represents an ARM-based realisation of this concept. This paper describes the initial details of the ProteanARM architecture and demonstrates some performance benefits gained through the use of custom function units. Our examples show a promising performance increase compared to a standard ARM processor, with reconfiguration costs being quickly amortised.

show abstract

A high-performance microarchitecture with hardware-programmable functional units

Cited by 230 publications

References 19 publications

Factors Influencing the Performance of a CPU-RFU Hybrid Architecture

Factors Influencing the Performance of a CPU-RFU Hybrid Architecture

Compiler Optimizations for Adaptive EPIC Processors

Initial Analysis of the Proteus Architecture

Contact Info

Product

Resources

About