A High Performance Reconfigurable Core for Motif Searching Using Profile HMM

Abstract

A common task in bioinformatics is

Combining execution pipelines to improve parallel implementation of HMMER on FPGA

“…Early proposals [12][13][14][15] of hardware accelerator for profile based similarity search considered an (over) simplified version of the algorithm in which the feed-back loop is ignored as such a simplification has a relatively limited impact on the actual quality of results of the algorithm.…”

A HMMER hardware accelerator using divergences

“…To do so, it implements a well-known DP algorithm called the Viterbi algorithm [16]. This algorithm calculates a set of DP matrices (corresponding to states M, I, and D) and vectors (corresponding to states N, B, E, C, and J) by means of a set of recurrence equations found in [10,12,13] and shown in Figure 2. Each state has transition probabilities to other states and the M and I states have emission probabilities in order to model the statistical behavior of the protein family.…”

“…As a result, it finds the best (most probable) alignment and its score for the query sequence with the given model. As the routine that implements the Viterbi algorithm in HMMER is the most time consuming of the search and comparison programs, most works [9][10][11][12][13][14]17] focus in accelerating its execution by proposing a pre-filter phase which only calculates the similarity score for the algorithm. Then, if the similarity score is good, the entire query sequence is reprocessed by the software to produce the alignment.…”

“…As the typical profile HMMs would be too long for its implementation to fit into an FPGA, the entire sequence processing is divided into several passes [9][10][11]14]. First-In First-Out memories are included inside the FPGA implementation to store the necessary intermediary data between passes.…”

“…Therefore, most authors have found useful to apply a first phase filter in order to discard poor scoring sequences prior to full processing. Some works apply heuristics, but the mainstream focuses in the use of FPGAbased accelerators [9][10][11][12][13][14] as this first phase filter. The filter retrieves the sequence score and, if it is acceptable, full reprocessing of the sequence is done in software.…”