A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications

Jain, Arpan; Ali, Amin Ahsan; Kiran, Sai; Abbas, Zia

doi:10.1109/iscas.2019.8702638

Cited by 17 publications

(3 citation statements)

References 11 publications

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“…The proposed work offers the least line sensitivity of 0.002%/V. The work reported in 18 offers the least temperature co-efficient of 11.6 ppm/ C. The current reference circuit described in Reference [20], offers the least power consumption of only 23 pW with the ultra-low current of only 20 pA. All the works compared in the table are performed under 0.18 μm process technology except the work described in Reference [8] which is performed in 0.35 μm process technology. All the designs are done approximately around 1.8 V supply voltage.…”

Section: Comparison With Existing Workmentioning

confidence: 99%

“…Here, K 5 is the aspect ratio of p-channel MOS transistor M 5 . Now substituting the value from Equation (18) in Equation ( 19), we get the final expression for reference current I ref as…”

Section: Proposed Circuit Topologymentioning

confidence: 99%

“…The circuit though consumes ultra‐low power of only 4.5 nW, but shows a little higher temperature coefficient 285 ppm/°C and also considerably large line sensitivity of 1.4%/V. By an unconventional method of dividing two temperature coefficients of a voltage and a resistor, 18 has generated a reference current of 50 nA showing a thermalresponse of only 11.6 ppm/°C to the temperature variation over a wide temperature range of −55°C through 125°C, with a low line sensitivity of 0.05%/V. However, the circuit incorporates a significantly complex transistor network for achieving stability in terms of supply and temperature variation.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 588 nW, 1 nA current reference circuit with extremely low (0.002%/V) line sensitivity over a wide supply voltage range and low temperature coefficient

Mukherjee

Upadhyay

et al. 2022

Int J Numerical Modelling

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A 1 nA current reference circuit is designed in semiconductor laboratory (SCL) 0.18 μm standard threshold voltage CMOS technology under 1.8 V power supply. The reference current is extremely immune to supply variation and shows a line sensitivity of 0.002%/V at post layout simulation level, over a wide range of supply variation from 0.5 V to 3.5 V. The line sensitivity is much smaller than any relevant data so far reported. In addition, it has a very low temperature coefficient of 214 ppm/°C over a temperature variation from −50°C to 50°C. The circuit consumes a total power of 588 nW. The reported results are also studied at various process corners and under variable process parameters like oxide thickness and threshold voltage of transistors. A satisfactory behaviour of the circuit is obtained in all cases. The accuracy of the simulation results is validated through quite close matching of the results with that obtained through rigorously developed theoretical models.

show abstract

Section: Comparison With Existing Workmentioning

confidence: 99%

“…Here, K 5 is the aspect ratio of p-channel MOS transistor M 5 . Now substituting the value from Equation (18) in Equation ( 19), we get the final expression for reference current I ref as…”

Section: Proposed Circuit Topologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 588 nW, 1 nA current reference circuit with extremely low (0.002%/V) line sensitivity over a wide supply voltage range and low temperature coefficient

Mukherjee

Upadhyay

et al. 2022

Int J Numerical Modelling

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show abstract

On the design of a reliable current reference for systems‐on‐chip

Torres

Roa

Rueda

2021

Circuit Theory & Apps

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Modern systems‐on‐chip use multiple current references to guarantee appropriate circuit biasing according to the required performance and power consumption. New reference topologies have emerged due to the necessity of ultra‐low‐power systems. Still, in the micro‐Ampere domain, the most common architectures are preferred in industry‐based applications, due to their reliability and accuracy. Motivated by the limited documentation and data associated with current references for SoCs, this work presents key observations in the design decisions, based on error contributions from the inherent elements of a reliable voltage‐to‐current reference architecture. Monte Carlo simulations show results for a 5 μA current reference, with inaccuracies at ±3σ of ±4% and ±1.3%, without and with trimming, respectively. Furthermore, two current references were fabricated using a 0.18 μm CMOS standard technology, in two different SoCs. Measurement results across voltage and temperature variations showed results for 50 μA ± 0.24% and 5 μA ± 0.8% current references without trimming.

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An area-efficient 1.96 nA 0.55 V 96 ppm/°C self-biased current reference using active resistor temperature coefficient compensation

Yang

Meng

2023

AEU - International Journal of Electronics and Communications

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A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications

Cited by 17 publications

References 11 publications

A 588 nW, 1 nA current reference circuit with extremely low (0.002%/V) line sensitivity over a wide supply voltage range and low temperature coefficient

A 588 nW, 1 nA current reference circuit with extremely low (0.002%/V) line sensitivity over a wide supply voltage range and low temperature coefficient

On the design of a reliable current reference for systems‐on‐chip

An area-efficient 1.96 nA 0.55 V 96 ppm/°C self-biased current reference using active resistor temperature coefficient compensation

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