A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

Chang, Meng-Fan; Sheu, Shyh-Shyuan; Lin, Ku-Feng; Wu, Che-Wei; Kuo, C. P.; Chiu, Pi-Feng; Yang, Yawei; Chen, Yu‐Sheng; Lee, Heng-Yuan; Lien, Chenhsin; Chen, F. T.; Su, Keng-Li; Ku, Tzu–Kun; Kao, Ming-Jer; Tsai, Ming-Jinn

doi:10.1109/jssc.2012.2230515

Cited by 91 publications

(41 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…4 presents the cell structure, mini-array, --curves, and bias conditions of a 1T1R-B cell using an HfO bipolar memristive device implemented via post back-end-ofline (BEOL) processing. The switching of resistance-states in bipolar memristive devices [37]- [40], [43]- [50], [53]- [56] is achieved by providing different voltage polarities across the two terminals (top and bottom plates) for SET and RESET operations. In a NOR-type 1T1R-B cell array, all memory cells in a given row share the same wordline (WL) and source-lines (SL), while all memory cells in a given column share the same bitline (BL).…”

Section: A Envm Cells Using Memristive Devicesmentioning

confidence: 99%

“…Fig. 15 presents the generated using two conventional reference-generation methods: two-reference-cell and "average of and " [40]. Variation in the reference cell can cause read failure when the read margin is insufficient to cover the offset of the sense amplifier, or when the distributions of and ( or ) overlap.…”

Section: ) Bl Clamping Voltage Versus Voltage Drop On Memristive Devicementioning

confidence: 99%

“…19(a) presents a typical memristive macro capable of achieving high-speed sensing and high read yield against process variations for current-mode sensing [40]. In that study, a parallel-series reference cell (PSRC) was proposed to eliminate the dependence of on a single tail-bit reference cell, which narrowed the distribution of due to variations in .…”

Section: Circuit Techniques For Read Operationsmentioning

confidence: 99%

See 2 more Smart Citations

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Chang

Lee

Chen

et al. 2015

IEEE J. Emerg. Sel. Topics Circuits Syst.

Self Cite

View full text Add to dashboard Cite

Memristive devices have shown considerable promise for on-chip nonvolatile memory and computing circuits in energyefficient systems. However, this technology is limited with regard to speed, power, VDDmin, and yield due to process variation in transistors and memrisitive devices as well as the issue of read disturbance. This paper examines trends in the design of device and circuits for on-chip nonvolatile memory using memristive devices as well as the challenges faced by researchers in its further development. Several silicon-verified examples of circuitry are reviewed in this paper, including those aimed at high-speed, area-efficient, and low-voltage applications.Index Terms-Memristive device, memristor, nonvolatile memory, recent developments in resistive memory (ReRAM), resistive RAM.

show abstract

Section: A Envm Cells Using Memristive Devicesmentioning

confidence: 99%

Section: ) Bl Clamping Voltage Versus Voltage Drop On Memristive Devicementioning

confidence: 99%

Section: Circuit Techniques For Read Operationsmentioning

confidence: 99%

See 1 more Smart Citation

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Chang

Lee

Chen

et al. 2015

IEEE J. Emerg. Sel. Topics Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…In non-volatile memory area, resistive RAM (ReRAM/memristor) is a promising candidate with fast write speed and low-power operation [8]. To avoid its read disturbance challenge, reliable read operation techniques are proposed [9,8], including a process-temperature-aware dynamic bitline bias scheme on a 4-Mb memristor fabricated chip [8].…”

Section: Introductionmentioning

confidence: 99%

“…To avoid its read disturbance challenge, reliable read operation techniques are proposed [9,8], including a process-temperature-aware dynamic bitline bias scheme on a 4-Mb memristor fabricated chip [8]. Li et al demonstrate a 1-Mb ternary content addressable memory (TCAM) test chip using 2-transistor/2-resistive-phase-change-storage (2T-2R) cells [10].…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient GPGPU architectures via collaborative compilation and memristive memory-based computing

Rahimi¹,

Ghofrani²,

Lastras-Montaño³

et al. 2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

View full text Add to dashboard Cite

Thousands of deep and wide pipelines working concurrently make GPGPU high power consuming parts. Energy-efficiency techniques employ voltage overscaling that increases timing sensitivity to variations and hence aggravating the energy use issues. This paper proposes a method to increase spatiotemporal reuse of computational effort by a combination of compilation and micro-architectural design. An associative memristive memory (AMM) module is integrated with the floating point units (FPUs). Together, we enable finegrained partitioning of values and find high-frequency sets of values for the FPUs by searching the space of possible inputs, with the help of application-specific profile feedback. For every kernel execution, the compiler pre-stores these high-frequent sets of values in AMM modules -representing partial functionality of the associated FPU-that are concurrently evaluated over two clock cycles. Our simulation results show high hit rates with 32-entry AMM modules that enable 36% reduction in average energy use by the kernel codes. Compared to voltage overscaling, this technique enhances robustness against timing errors with 39% average energy saving.

show abstract

Role of the Electrode Material on the RESET Limitation in Oxide ReRAM Devices

Schönhals

Rosário

Hoffmann‐Eifert

et al. 2017

Adv Elect Materials

View full text Add to dashboard Cite

NVM). Of those, redox-based resistive switching memory [2] (ReRAM) is of high interest, in particular for application in new storage class memory, [3,4] as well as a technology for scaled embedded NVM. [5][6][7] Recent results regarding switching speed, [8] cycling endurance, [9] scalability, [10] and integration [11] indicate an outstanding potential of metal-oxide based ReRAM technology for the above mentioned memory applications. Additionally, scenarios for use of ReRAM devices in novel application fields as neuromorphic computing or logic-in-memory have been demonstrated recently. [12,13]

show abstract

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

Cited by 91 publications

References 25 publications

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Energy-efficient GPGPU architectures via collaborative compilation and memristive memory-based computing

Role of the Electrode Material on the RESET Limitation in Oxide ReRAM Devices

Contact Info

Product

Resources

About