A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems

Abstract

This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the throughput requirement of 2.59 Giga-samples/s, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced. Specifically, the radix-16 butterfly processing element consists of two cascaded parallel/pipelined radix-4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers. Moreover, a conflict-free multibank memory addressing scheme is devised to support up to 16-way parallel and normal-order data input/output. Without needing to reorder the input/output data, this scheme helps a high-throughput design result. Equipped with those new performance-boosting techniques, overall the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that whole FFT processor area is mm , and the power consumption is 42 mW with 90 nm process. The SQNR performance is 57 dB with 12-bit wordlength implementation.Index Terms-Fast Fourier transform (FFT), non-conflict memory addressing scheme, OFDM, radix-16 FFT, WPANs.

High-throughput Low-complexity Mixed-radix FFT Processor using a Dual-path Shared Complex Constant Multiplier

“…In addition, there is no need to allocate memory to store the twiddle factor. Table 3 shows the performance comparisons between the proposed 512-point eight-parallel mixed-radix 2 4 /2 3 MDF FFT/IFFT processor using CCM and several existing 512-point FFT processors [9][10][11]. The results show that the proposed FFT processor obtains much better SQNR performance than that of [9].…”

“…In addition, we propose the architecture of a dual-path shared multi-layer canonical signed digit (CSD) complex constant multiplier (DPS-MLCCM) to reduce the hardware complexity for TF multiplication of parallel FFT processors. The proposed FFT processor provides better throughput and less hardware complexity compared to previous designs [9][10][11]. The rest of this paper is organized as follows.…”

A Low-Memory-Access Length-Adaptive Architecture for 2 $$^n$$ n -Point FFT

“…Furthermore, Table 6 illustrates the performance comparison of this work with five recent state-of-the-art FFT chip designs [18,21,24,26], and [17]. The designs [24] and Table 6 Performance comparison with modern long-length FFT designs Design Lin et al [24] Lee and Park [21] Hung et al [18] Lin et al [26] Huang and Chen [17] T [21] are respectively the representatives of the cached-memory and the pipeline architecture.…”

“…From the thorough analyses of memory access required for FFT operations, obvious memory access reduction can be predicted by the proposed high-radix-first algorithm as contrary to the memory-based architecture in [18]. The second one is that we adopt the design concept of programmable processors to provide the flexibility in dynamically configuring the hardware for computing variable-length FFT without sacrificing the hardware utilization as contrary to the feed-forward architecture in [17]. Besides, the author proposed an efficient and flexible length-adaptive FFT architecture to implement the presented high-radix-first algorithm.…”

Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures

“…However, much fewer works are dedicated to bit-reversal circuit design in the literature until recent years, compared to the amount of works on FFT architecture designs. For general memory-based FFT architectures, there are memory addressing schemes [14][15][16], which facilitate natural-order FFT outputs. For pipelined FFT, bit-reversal circuits must support continuous-flow processing for the consideration of seamless generation of FFT outputs, due to contiguous inputs.…”