A high-voltage monolithic isolator for a communication network interface

Akiyama, Nobuyuki; Kojima, Yasuyuki; Nemoto, M.; Yukutake, S.; Iwasaki, Takaya; Amishiro, M.; Kanekawa, Nobuyasu; Watanabe, Atsuo; Takeuchi, Yukiko

doi:10.1109/16.998600

Cited by 16 publications

(9 citation statements)

References 2 publications

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“…However, optical couplers do not provide a sufficiently high transmission rate and consume a large amount of power, while transformers are too bulky [1–6]. Although monolithic isolators avoid these problems [7–10], their isolation voltage is insufficient for telecommunication network systems.…”

Section: Introductionmentioning

confidence: 99%

4‐kV 100‐Mbps monolithic isolator on SOI with trench isolation for wideband networks

Hashimoto

Yukutake

Kanekawa

et al. 2013

IEEJ Transactions Elec Engng

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Two types of monolithic isolator on a silicon-on-insulator (SOI) with trench isolation have been fabricated. One is a multitrench isolator with polysilicon resistors in which two circuit areas are isolated using thirty-four 0.4-μm-wide trenches on an SOI. The inequality in the voltages applied to the trenches is reduced by using polysilicon resistors parallel to the trenches, which increases the isolation voltage from 2.6 to 4.0 kV. The other is a spiral wide-trench isolator in which two circuit areas are isolated using two spiral 10-μm-wide trenches. Monocrystalline silicon is used as a resistor to reduce the inequality in the trench voltages. Signals are transmitted between the two circuit areas through two series of high-voltage capacitors: silicon on buried oxide and a third metal are used as electrodes. A network interface large-scale integration (LSI) with a four-channel isolator was fabricated using multitrench isolation. It provides 4-kV isolation and supports 100-Mbps transmission.

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Section: Introductionmentioning

confidence: 99%

4‐kV 100‐Mbps monolithic isolator on SOI with trench isolation for wideband networks

Hashimoto

Yukutake

Kanekawa

et al. 2013

IEEJ Transactions Elec Engng

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“…Figure 2(a) shows the on-chip integrated isolation structure. [29][30][31][32] Regions 1 and 2 are silicon active areas isolated from each other and located symmetrically. In Fig.…”

Section: Isolation Structure and Issuementioning

confidence: 99%

“…Figure 2(b) is a photograph of the isolator chip. [30][31][32][33][34] Analog circuits are shown in the left region and the digital circuit is in the right region.…”

Section: Isolation Structure and Issuementioning

confidence: 99%

“…However, the breakdown voltage between regions 1 and 2 was 1.5 kV ac . [30][31][32][33][34] This result is supposed to originate from the complexity of the multiple-trench-gap structure. The objectives of this work are to analyze this isolation structure, understand the differences between the expected and experimental results, and show a theoretical guideline for improvement.…”

Section: Isolation Structure and Issuementioning

confidence: 99%

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Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

Takeuchi¹,

Kuroda²,

Sugawa³

2015

Jpn. J. Appl. Phys.

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We analyzed the shared voltages of multiple trench gaps on a silicon-on-insulator (SOI) substrate and showed the conditions for improving the breakdown voltage surrounded by these isolated structures. We introduced a unified impedance model instead of the capacitive model of trench gaps and determined the effective conditions for improving the breakdown voltage. The first condition is to reduce the impedance of trench gaps. In this case, the leak current gives a low limit of trench gap resistance. The second condition is to increase the substrate resistance. As silicon substrate resistance is not very high, this condition is not useful for the silicon substrate, but for other materials such as ceramics. We confirmed the effectiveness of these conditions from the simulation and experimental results of a fabricated chip.

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“…A multiple trench gap structure is good solution. Using this structure, an on-chip 2.3-kV 100-MHz multi-channel monolithic isolator IC has been achieved [1][2]. Further, that the breakdown voltage is improved to 4.0-kV without changing the chip size by being biased by the voltage divided by the Poly-Si resistors [3][4].…”

Section: Introductionmentioning

confidence: 99%

Analysis of the Breakdown Voltage of an Area Surrounded by the Multi-trench Gaps in a 4kV Monolithic Isolator for a Communication Network Interface

Takeuchi¹,

Kuroda²,

Sugawa³

2014

Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials

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We analyzed the conditions to improve the dielectric breakdown voltage in the area surrounded by the buried oxide (BOX) film and the buried multiple trench gaps on the SOI substrate surface. We use an impedance model and determine the conditions to improve the breakdown voltage. One is to increase the impedance of the BOX, The other one is to reduce the impedance of the trench gaps. We confirmed them by simulation and the experimental results.

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A high-voltage monolithic isolator for a communication network interface

Cited by 16 publications

References 2 publications

4‐kV 100‐Mbps monolithic isolator on SOI with trench isolation for wideband networks

4‐kV 100‐Mbps monolithic isolator on SOI with trench isolation for wideband networks

Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

Analysis of the Breakdown Voltage of an Area Surrounded by the Multi-trench Gaps in a 4kV Monolithic Isolator for a Communication Network Interface

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