A highly-integrated CMOS analog baseband transceiver with 180MSPS 13b pipelined CMOS ADC and dual 12b DACs

Abstract

The 180MSPS, 13b CMOS pipelined ADC of a transceiver is implemented without a dedicated track-and-hold stage and utilizes a front-end 2.5b stage with matched MDAC/comparator tracking circuits. The ADC demonstrates ENOB of 10.6b at 15MHz and 9.7b at 100MHz. It employs a lowjitter delay-lock loop for its phasing. The dual I/Q 12b 180MSPS DACs show over 62dB SFDR over the Nyquist band by utilizing a dynamic linearity enhancing architecture.

15.6 12b 250MS/S pipelined ADC with virtual ground reference buffers

“…In the presented ADC, the buffers replace existing reference buffers, thus incurring insignificant penalty; while off-chip bypass capacitors can be used in conventional circuits to ease the reference buffer requirements [20][21][22], on-chip high-speed buffers are strongly desired in highspeed, high-SNR ADCs to avoid reference voltage ringing [23][24][25]. More detailed analysis of the buffer bandwidth and noise is presented in the next subsection.…”