A highly manufacturable corner rounding solution for 0.18 μm shallow trench isolation

Chang, C.P.; Pai, C.S.; Baumann, F.H.; Liu, C.T.; Rafferty, C. S.; Pinto, M.R.; Lloyd, Emily; Bude, M.; Klemens, F.; Miner, J.F.; Cheung, Kin P.; Colonell, Jennifer; Lai, Wang; Vaidya, H.; Hillenius, S.J.; Liu, R.C.; Clemens, J.T.

doi:10.1109/iedm.1997.650470

Cited by 25 publications

(4 citation statements)

References 4 publications

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“…The thickness of the nitride layer is determined by the desired post-CMP step height between the active and isolation areas [13]. It reduces RIE damage to the trench walls [15], rounds the bottom trench corners thus reducing mechanical stress, and rounds the top trench corner for improved device performance [16]. Next, isolation trenches with depth of 250-700 nm are etched into the substrate with chloride-based (e.g., SiCl 4 ) plasma.…”

Section: Shallow Trench Isolationmentioning

confidence: 99%

Shallow Trench Isolation Chemical Mechanical Planarization

Stefanov

Schwalke

2007

Microelectronic Applications of Chemical Mechanical Planarization

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Section: Shallow Trench Isolationmentioning

confidence: 99%

Shallow Trench Isolation Chemical Mechanical Planarization

Stefanov

Schwalke

2007

Microelectronic Applications of Chemical Mechanical Planarization

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“…The pre-CMP rounding techniques have included Hydrogen annealing 2I and liner oxidation [1] that involves wet or dry oxidation at the proper temperature, time, ambient, and pre-clean. The post-CMP rounding techniques have involved high temperature wet oxidation [3,4], but if improperly designed can generate stress and lead to dislocation formation in the high stress areas.…”

Section: Introductionmentioning

confidence: 99%

Stress minimization of corner rounding process during STI

Olsen¹,

Nouri²,

Rubin³

et al. 1999

SPIE Proceedings

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For sub 0.25 micron CMOS processes, Shallow Trench Isolation (STI) is required because of its planarity, high packing density and low junction edge capacitance. After trench etch in the STI process, the top corner of the trench must be rounded in order to achieve stable device performance (no kink in the subthreshold slope), reduce inverse narrow width effects and maintain good gate oxide integrity. Several methods of rounding the trench corners have been proposed. A post CMP oxidation step to round the top corner trench has been shown to consume too much of the silicon active area and may not be suitable for sub-0. 1 8m technologies. Furthermore, the post-CMP oxidation can generate a lot of stress even at high (>1075°C) temperatures. It has been shown that a 50 nm radius of curvature provides stable device data [1J and good gate oxide integrity with minimum consumption of the active area (DeltaW). In this paper, we have shown that this radius can be achieved with minimal stress generation using a properly optimized Rapid Thermal Oxidation (RTO) (liner oxide) before oxide fill. Through both 2D oxidation modeling and experimental verification we have shown that an optimum oxidation temperature can be found when coupled with an undercut of the buffer oxide under the silicon nitride mask. Temperature is the primary parameter for rounding of the top corner during oxidation while undercut of the buffer oxide lowers the minimum temperature for a given rounding. A 50 nm radius of curvature can be achieved by the balance of the two parameters. This radius of curvature has been shown to suitable for 0. 15 micron technology and beyond.

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“…2(b). The comer rounding is formed by the pull-back and hydrogen annealing that leads to the silicon migration and crystal orientation reform from (100) to (1 1 1) [6]. This crystal orientation reform increases the oxide growth rate at the top and bottom comer of the trench, resulting in uniform oxide growth along the trench surface and higher reliability.…”

Section: Process Discriptionmentioning

confidence: 99%

A novel process technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing

Kim

Roh²,

Kim³

et al.

Proceedings of the 13th International Symposium on Power Semiconductor Devices &Amp; ICs. IPSD '01 (IEEE Cat. No.01CH37216)

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A novel process technique for fabricating trench DMOSFETs using 3 mask layers is realized in order to obtain cost-effective production capability, higher cell density and current driving capability, and higher reliability.A unit cell with a cell pitch of 2.3-2.4 pm and a channel density of 1 00McelVin2 are obtained. Specific on-resistance is 0.36 mR.cm2 with a blocking voltage of 43 V. The time to breakdown of gate oxide grown on the hydrogen annealed trench surface is much longer than that of the gate oxide grown on the non-hydrogen annealed trench surface

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A highly manufacturable corner rounding solution for 0.18 μm shallow trench isolation

Cited by 25 publications

References 4 publications

Shallow Trench Isolation Chemical Mechanical Planarization

Shallow Trench Isolation Chemical Mechanical Planarization

Stress minimization of corner rounding process during STI

A novel process technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing

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