A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer

Morris, Gerald R.; Prasanna, Viktor K.; Anderson, Richard

doi:10.1109/fccm.2006.8

Cited by 41 publications

(28 citation statements)

References 12 publications

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“…The three most notable examples are a molecular dynamics application [Kindratenko and Pointer 2006;Scrofano et al 2006], a full CG solver [Morris et al 2006], and a traffic simulation engine [Tripp et al 2005]. None of these efforts have considered requirements for future systems attempting to leverage FPGAs.…”

Section: Related Workmentioning

confidence: 99%

“…This led researchers to begin by focusing on kernel operations that are used in HPC and can be provided through a standard library interface. Operations from BLAS [Underwood and Hemmert 2004;Zhuo and Prasanna 2004;Dou et al 2005;Zhuo and Prasanna 2005a;Zhuo and Prasanna 2005b] to FFTs [Hemmert and Underwood 2005] to the sparse matrix operations at the core of an iterative solver [deLorimier and DeHon 2005;Zhuo and Prasanna 2005c] and even a full CG solver [Morris et al 2006] have been studied. The fundamental challenge for each of these efforts is the communications with the host.…”

Section: Introductionmentioning

confidence: 99%

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Architectures and APIs: Assessing Requirements for Delivering FPGA Performance to Applications

Underwood¹,

Hemmert²,

Ulmer³

2006

ACM/IEEE SC 2006 Conference (SC'06)

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Reconfigurable computing leveraging field programmable gate arrays (FPGAs) is one of many accelerator technologies that are being investigated for application to high performance computing (HPC). Like most accelerators, FPGAs are very efficient at both dense matrix multiplication and FFT computations, but two important aspects of how to deliver that performance to applications have received too little attention. First, the standard API for important compute kernels hides parallelism from the system. Second, the issue of system architecture is virtually never addressed. This paper explores both issues and their implications for applications. We find that high bandwidth, low latency connectivity can be important, but the right API can be even more important.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Architectures and APIs: Assessing Requirements for Delivering FPGA Performance to Applications

Underwood¹,

Hemmert²,

Ulmer³

2006

ACM/IEEE SC 2006 Conference (SC'06)

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“…A profile of CG 4 shows that it spends more than 95 percent of the execution time in SMVM (line 6 of the CG algorithm), so we targeted this module for the FPGA. Figure 3 shows our high-level CG design.…”

Section: High-level Cg Designmentioning

confidence: 99%

“…754 floating-point units, 1 molecular dynamics kernels, 2 linearalgebra routines, 3 and sparse matrix solvers. 4 Mapping two sparse matrix solvers onto an FPGA-augmented reconfigurable computers (RC) demonstrated more than a twofold speedup over software.…”

mentioning

confidence: 99%

Sparse Matrix Computations on Reconfigurable Hardware

Prasanna

Morris

2007

Computer

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Computer P u b l i s h e d b y t h e I E E E C o m p u t e r S o c i e t ycircuit on an FPGA. In practice, area, clock rate, and I/O are the primary constraints. RECONFIGURABLE COMPUTERSFirst proposed by Gerald Estrin 6 in 1960, the RC is a "fixed plus variable structure" computer that can be "temporarily distorted into a problem-oriented specialpurpose computer." The RC languished in relative obscurity for more than 30 years. However, the FPGA has precipitated a reawakening, and RCs that use generalpurpose processors (GPPs) and FPGAs as the fixed-plusvariable structure have recently become available. The fine-grained resolution of FPGAs allows reconfiguring the hardware for the specific problem at hand. For applications that have some combination of large-strided or random data reuse, streaming, parallelism, or computationally intensive loops, RCs can achieve higher performance than GPPs.High-level-language-to-HDL compilers provide features such as pipelined loops and parallel code blocks that allow migrating FPGA-based development out of the hardware design world and into the HLL programming world. The goal is to create deeply pipelined, highly parallelized designs without, as SRC Computers' CEO Jon Huppenthal terms it, "a hardware buddy." figurable computing conference in August 2005. In concept, researchers can, for example, use C to develop an

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“…One such property, the time invariance of A (A is not updated during CG iterations) leads to an obvious optimisation used in [6]: copy A to the hardware accelerator only once for multiple iterations. We use this property to statically schedule the entire algorithm (Section IV).…”

mentioning

confidence: 99%

An efficient sparse conjugate gradient solver using a Beneš permutation network

Chow

Grigoras

Burovskiy

et al. 2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-The conjugate gradient (CG) is one of the most widely used iterative methods for solving systems of linear equations. However, parallelizing CG for large sparse systems is difficult due to the inherent irregularity in memory access pattern. We propose a novel processor architecture for the sparse conjugate gradient method. The architecture consists of multiple processing elements and memory banks, and is able to compute efficiently both sparse matrix-vector multiplication, and other dense vector operations. A Beneš permutation network with an optimised control scheme is introduced to reduce memory bank conflicts without expensive logic. We describe a heuristics for offline scheduling, the effect of which is captured in a parametric model for estimating the performance of designs generated from our approach.

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A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer

Abstract: Supercomputer companies such as Cray, Silicon Graphics, and SRC Computers now offer reconfigurable computer (RC)

Cited by 41 publications

References 12 publications

Architectures and APIs: Assessing Requirements for Delivering FPGA Performance to Applications

Architectures and APIs: Assessing Requirements for Delivering FPGA Performance to Applications

Sparse Matrix Computations on Reconfigurable Hardware

An efficient sparse conjugate gradient solver using a Beneš permutation network

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A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer

Abstract: Supercomputer companies such as Cray, Silicon Graphics, and SRC Computers now offer reconfigurable computer (RC)

Cited by 41 publications

References 12 publications

Architectures and APIs: Assessing Requirements for Delivering FPGA Performance to Applications

Architectures and APIs: Assessing Requirements for Delivering FPGA Performance to Applications

Sparse Matrix Computations on Reconfigurable Hardware

An efficient sparse conjugate gradient solver using a Bene&#x0161; permutation network

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Resources

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An efficient sparse conjugate gradient solver using a Beneš permutation network