A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC

Kim, Jungho; Kim, Young-Hwa; Kim, Kwang‐Seok; Yu, Wonsik; Cho, SeongHwan

doi:10.1109/tcsii.2015.2415631

Cited by 24 publications

(14 citation statements)

References 8 publications

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“…Using the measured data, we obtain the number of bits N Bit = log 2 (maximum input range/resolution) to be 9.88 bits. Taking nonlinearity into consideration, we obtain the equivalent number of linear bits N linear = N Bit − log 2 (INL + 1) to be 8.15 bits [ 23 ].…”

Section: Measured Resultsmentioning

confidence: 99%

“…The work in [ 21 ] realizes a cyclic TDC using a hardware description language (HDL) which allows chip synthesis with automatic place-and-route tools. The work in [ 23 ] presents a two-step TDC based on a pseudo-differential TVC and a 6-bit SAR ADC. This work achieves a high conversion rate of 120 MS/s with a power of 3.73 mW.…”

Section: Measured Resultsmentioning

confidence: 99%

“…Because long-time measurements are adversely affected by accumulated jitter and mismatch-related nonlinearity, realizing a sensor achieving a large input range is challenging [ 15 ]. Various strategies are reported to increase input range while achieving fine resolution, including two-dimensional (2-D) and three-dimensional (3-D) Vernier structure [ 16 , 20 ], cyclic Vernier [ 21 ], gated-Vernier oscillator [ 22 ], and a time-to-voltage converter (TVC) [ 23 ].…”

Section: Introductionmentioning

confidence: 99%

“…Another approach used to extend the performance of the TDC is using a time-to-voltage converter (TVC) followed by a successive approximation register (SAR) analog-to-digital converter (ADC) [ 23 ]. This approach converts the time interval into a voltage, and then quantizes the voltage by the ADC.…”

Section: Introductionmentioning

confidence: 99%

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A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique

Nguyen

Duong

Chung

et al. 2018

Sensors

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Herein, we present a low-power cyclic Vernier two-step time-to-digital converter (TDC) that achieves a wide input range with good linearity. Since traditional approaches require a large area or high power to achieve an input range >300 ns, we solve this problem by proposing a simple yet efficient TDC suitable for time-of-flight (TOF) sensors. In previous studies using the cyclic structure, the effect of startup time on the linearity of the TDC is not described. Thus, the achievable linearity has been limited when the TDC is used for applications requiring a high input range. We solve this problem by using a simple yet effective technique to compensate. The proposed technique is realized using (1) digitally-controlled oscillators (DCOs) that have dual frequency control and matched startup time; (2) an alignment detector that performs startup time correction by proper timing control; and (3) a fully symmetric arbiter that precisely detects the instant of edge alignment. To achieve a fine resolution for the cyclic Vernier TDC, we design two closely-matched DCOs with dual frequency control. The alignment detector performs the critical task of cancelling startup time via timing control. The detector is delay-compensated by using a dummy to provide matched loading for the two DCOs. To enhance the detection speed under low power, a current-reuse approach is employed for the arbiter. The TDC is fabricated using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in a compact chip area of 0.028 mm2. Measured results show a dynamic range of 355 ns and a resolution of 377 ps. When the result is applied for TOF sensing, it corresponds to a distance range of 53.2 m and a resolution of 5.65 cm. Over a relatively large input range, good linearity is achieved, which is indicated by a DNL of 0.28 LSBrms and an INL of 0.96 LSBrms. The result corresponds to root mean square (RMS) error distance of 5.42 cm. The result is achieved by consuming a relatively low power of 0.65 mW.

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Section: Measured Resultsmentioning

confidence: 99%

Section: Measured Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique

Nguyen

Duong

Chung

et al. 2018

Sensors

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“…In order to demonstrate the validity of the proposed model, the predicted jitter by Eq. (30) has been compared to the simulated one (see Fig. 19-circle marker).…”

Section: ) Vcro Jitter Due To White Noisementioning

confidence: 99%

Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors

Vornicu

Carmona-Galán

Rodríguez-Vázquez

2017

IEEE Trans. Circuits Syst. I

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Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-to-digital converter (TDC) at pixel level. A feasible approach to a compact implementation of the TDC is to use the multiple phases of a voltage-controlled ring-oscillator (VCRO) for the finest bits. The VCRO becomes central in determining the performance parameters of a d-ToF image sensor. In this paper we are covering the modeling, design and measurement of a CMOS pseudo-differential VCRO. The oscillation frequency, the jitter due to mismatches and noise and the power consumption are analytically evaluated. This design has been incorporated into a 64×64-pixel array. It has been fabricated in a 0.18µm standard CMOS technology. Occupation area is 28×29μm 2 and power consumption is 1.17mW at 850MHz. The measured gain of the VCRO is of 477MHz/V with a frequency tuning range of 53%. Moreover it features a linearity of 99.4% over a wide range of control frequencies, namely from 400MHz to 850MHz. The phase noise is of-102dBc/Hz at 2MHz offset frequency from 850MHz. The influence of these parameters in the performance of the TDC has been measured. The minimum time bin of the TDC is 147ps with a RMS DNL/ INL of 0.13/ 1.7LSB.

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A 0.008‐mm², 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

Kim

Shon

Kim

2016

Circuit Theory & Apps

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SummaryThis paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm2. The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.

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A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC

Cited by 24 publications

References 8 publications

A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique

A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique

Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors

A 0.008‐mm², 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

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A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC

Cited by 24 publications

References 8 publications

A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique

A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique

Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

Contact Info

Product

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A 0.008‐mm², 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture