A Lateral Trench Dual Gate Power MOSFET on Thin SOI for Improved Performance

Abstract

In this paper, an integrable lateral trench dual gate metal-oxide-semiconductor (LTDGMOS), a power MOSFET on silicon-on-insulator (SOI) is presented. The device consists of two separate trenches built in a thin SOI substrate in which two gates are placed on both sides of the P-body region. The trench dual gate structure not only enhances the drain current due to parallel conduction of two channels but also causes reduced-surface-field effect in the device resulting significant improvement in all performance parameters. The performance of the proposed device is analyzed and compared with that of the conventional lateral MOSFET using 2D numerical simulations. The LTDGMOS provides 2.5 times higher output current, 27% decrease in threshold voltage, 29% reduction in specific ON-resistance (Ron-sp), 74% improvement in peak transconductance, 50% increase in breakdown voltage (Vbr), and 28% reduction in gate-drain charge density (Qgd) as compared to the conventional counterpart for the same cell pitch. The superior Vbr, Ron-sp, and Qgd of the proposed device yield an improvement of 300% and 50% in the figure-of-merits Vbr 2/Ron-sp and Ron-sp .Qgd, respectively over the conventional device.

Design considerations of a novel Triple Oxide Trench Deep Gate LDMOS to improve self‐heating effect and breakdown voltage

“…The vertical breakdown voltage (BV vertical ) is defined as the following Equation () [30–34]: where V si is the voltage sustained by the SOI film, V bureid is the voltage sustained by the BOX, and V sub is the voltage sustained by the substrate. The vertical distributions of the electric fields for both the TOTDG‐LDMOS and C‐LDMOS devices at x = 9.99 μm are illustrated in Figure 5.…”

“…The vertical breakdown voltage (BV vertical ) is defined as the following Equation (1) [30][31][32][33][34]:…”

High performance selective buried double gate power MOSFET

“…The ON resistance is calculated as the ratio of V ds and I ds from the linear region of the output characteristic curve for both the devices [18,19]. Being the major contribution of ON resistance in the trench MOSFET, the drift region resistance and thus the total resistance in the proposed SBGPMOS is reduced by a high drift doping concentration of 5×10 15 cm −3 in the proposed structure as compared to 5.6×10 14 cm −3 in the conventional one.…”

Modeling and Simulation of Power MOSFET Using Orcad-Pspice

“…With a few minor exceptions, remarkable agreement has been demonstrated when product characterization and simulated MOSFET behavior is compared [6].…”