A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing

Kiamehr, Saman; Firouzi, Farshad; Tahoori, Mehdi B.

doi:10.1109/ets.2013.6569356

Cited by 9 publications

(4 citation statements)

References 28 publications

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“…. 4 ( − 3)) on 1 (), 4 (), 7 (), 10 (); iii) the state of the LFSR at 3 shift CKs after the current state of the LFSR (i.e., 1 ( + 3). .…”

Section: A Case Of 1 Substitute Test Vectormentioning

confidence: 99%

“…Together with several benefits (improved performance, decreased cost per function, etc. ), this poses serious challenges in terms of test and reliability [1,2,3,4,5,6,7]. In particular, during at-speed test of high performance microprocessors, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during in field operation [5,8,9,11,13,14,15].…”

Section: Introductionmentioning

confidence: 99%

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Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Omaña

Rossi

Fuzzi

et al. 2017

IEEE Trans. VLSI Syst.

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Abstract-The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel, scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the Logic BIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target Fault Coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared to recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC.

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“…. 4 ( − 3)) on 1 (), 4 (), 7 (), 10 (); iii) the state of the LFSR at 3 shift CKs after the current state of the LFSR (i.e., 1 ( + 3). .…”

Section: A Case Of 1 Substitute Test Vectormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Omaña

Rossi

Fuzzi

et al. 2017

IEEE Trans. VLSI Syst.

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“…The emerging resistive random access memory (RRAM) has attracted research enthusiasm from materials, devices and chips. Until now, this research mainly focused on improving performance including high to low resistance window, data retention, endurance, etc, and the fabricated chips mainly addressed the circuit and architecture issues for high density standalone applications [6][7][8]. This paper proposed a SRAM chip for keys storage with physical security features of resisting fully invasive attacks, side-channel attacks, malicious writes and data interception, etc.…”

Section: Introductionmentioning

confidence: 99%

High Speed Novel Design of Sram for Highly Reliable Applications

2019

IJITEE

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Modern ICs are enormously complicated due to decrease in device size and increase in chip density involving several millions of transistors per chip. The rules for manufactured leads to a tremendous increase in complexity due to the amount of power dissipation are increased. In this paper, the design of novel SRAM is implemented for the highly reliable applications. For high-speed memory applications such as cache, a SRAM is often used. Power consumption is the key parameter for an SRAM memory design (SRAM). New tag generation system designed for integrity checking of SRAM. A single read operation to a crossbar SRAM that can be used for integrity checking. Reliability of the system is measured for varying conditions of device parameters, operating temperatures, load resistances, and read voltage.

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“…Test operations consume more power than normal operations because test patterns make large transitions in circuits under testing [1,2,3]. Timing failures that don't occur in normal operations can be generated by these test operations and these make the overkill problem [4,5]. For this reason, research on the reduction of peak power during testing is required.…”

Section: Introductionmentioning

confidence: 99%

A novel X-filling method for capture power reduction

Kim

Lim

et al. 2017

IEICE Electron. Express

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This paper proposes a X-filling method that reduces capture power during scan-based testing. The proposed method classifies scan cells for dividing the scan cells into some groups. Then, based on the divided groups, X-bits are filled simultaneously to reduce the computation time. Since the proposed method uses a novel grouping algorithm and fills X-bits based on groups, the proposed method reduces switching activity and computation time when compared with conventional X-filling methods. The simulation results show that the proposed method reduces the switching activity up to 70% and the number of simulations for the X-filling up to 52% compared with that of conventional X-filling methods.

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A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing

Cited by 9 publications

References 28 publications

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

High Speed Novel Design of Sram for Highly Reliable Applications

A novel X-filling method for capture power reduction

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