A low energy switching scheme for SAR ADC with MSB-splitting DAC structure

Shifting the sampled input signal in successive approximation register analog‐to‐digital converters to reduce the digital‐to‐analog converter switching energy and area

“…Successive approximation register (SAR) analog‐to‐digital converters (ADCs) generally consume low power in medium resolutions and bandwidths, 1–8 and this property makes them suitable for an extensive variety of applications specifically in energy‐limited applications, 1 multichannel neural recording systems, 2 wearable sensors, 3 and low energy wireless sensor network chips 4 . In charge‐redistribution SAR ADCs, the power consumption of the capacitor switching in the digital‐to‐analog converter (DAC) usually is dominant 1–5,9–15 .…”

“…In charge‐redistribution SAR ADCs, the power consumption of the capacitor switching in the digital‐to‐analog converter (DAC) usually is dominant 1–5,9–15 . Recently, several techniques have been presented to reduce the DAC switching energy and capacitor size 1–26 …”

“…A two‐step architecture with an MSB capacitor splitting and monotonic switching scheme is used in Ding et al 5 to reduce the total capacitance size and DAC area. The MSB‐splitting DAC and the LSB‐down techniques are combined in Wang and Wu 6 for switching energy reduction. In Zhou et al, 7 a two‐step quantization results in both switching energy and capacitor area reductions.…”