A Low Power Deterministic Test Using Scan Chain Disable Technique

A response compactor for extended compatibility scan tree construction

“…However, its test application time is very long and test data volume is quite large. The techniques in [3][4][5] reduce the test application time and test data volume in scan test by cutting the scan chain into some sub-chains to shift in the test vector simultaneously. These multiple scan chain technologies increase the number of inputs and outputs, and occupy the limited number of the pins in a chip.…”

“…The head nodes nil, ni2 of their maximal unique sub-paths have the same sequential depth and they have no common parent node. 4. The head nodes nil, ni2 have a common parent node and there exists a sibling node excluding themselves.…”

DCScan: A Power-Aware Scan Testing Architecture

“…Many techniques [5][6][7][8][9][10][11][12][13][14][15] have been proposed to reduce switching activity during test. Test vectors in a test set or scan cells are reordered for minimal power consumption [5][6][7][8] .…”

“…The techniques in [9][10] reduce test power by specifying each don't care bit in the test cubes with appropriate value 0 or 1. There also exist some methods [11][12][13][14] that reduce power dissipation by using scan chain disabling technique. However, they did not consider test application time and test data volume reduction.…”