A low‐power, low‐data‐rate efficient ADC with hybrid exponential‐linear transfer curve for bio‐potential recording systems

Abstract

Summary A digital‐ramp hybrid exponential‐linear analog‐to‐digital converter (ADC) is presented in this paper, which is attractive, where a high dynamic range (DR) is required. It is especially applicable for sampling neural (bio‐potential) signals, as most of the neural signal data are concentrated on higher side of the amplitude range. By the exponential quantization function for low signal amplitudes, the background noise that disperses in lower amplitudes will be reduced. For higher signal amplitudes, the exponential function optionally switches to linear function at an adjustable voltage threshold, to reduce required number of bits for those high amplitudes, as well. As a result of this exponential‐linear hybrid operation, the total data rate and the power required for data transmission are decreased. A prototype 8‐bit counter‐based exponential ADC is designed and simulated in 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS). The 20‐KS/s ADC achieves a DR of 66 dB, occupies 0.036 mm2 area, and consumes 6.4‐μW power from a 1.8‐V supply. Integral nonlinearity (INL) and differential nonlinearity (DNL) that are redefined to be compatible with nonlinear ADCs are 3.2 and 0.88 least significant bits (LSBs), respectively.

A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

“…The demand for high-speed and low-power ADCs for battery-operated systems like medical imaging, CMOS image sensors, mobile, and wearable devices are increased substantially in recent years. [1][2][3] Among various ADCs' architectures like pipelined ADCs, deltasigma ADCs, and single-slope ADCs, the successive approximation register (SAR) ADCs are spotted for excellent power efficiency. [4][5][6][7] Furthermore, as the feature size of CMOS devices are scaling down, the conversion rate of SAR ADCs improves.…”

“…Analog‐to‐digital converters (ADCs) bridge the physical world to the digital domain. The demand for high‐speed and low‐power ADCs for battery‐operated systems like medical imaging, CMOS image sensors, mobile, and wearable devices are increased substantially in recent years 1–3 . Among various ADCs' architectures like pipelined ADCs, delta‐sigma ADCs, and single‐slope ADCs, the successive approximation register (SAR) ADCs are spotted for excellent power efficiency 4–7 .…”