A low-power programmable DSP core architecture for 3G mobile terminals

Kumura, Takahiro; Ishii, D.; Ikekawa, M.; Kuroda, I.; Yoshida, Makoto

doi:10.1109/icassp.2001.941090

Cited by 10 publications

(10 citation statements)

References 8 publications

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“…Assuming that the generator polynomial is described by (2), the convolutional encoding is performed by XOR operations of the (K − 1)-bit shifted data, the A-bit shifted data, the B-bit shifted data, the C-bit shifted data, and the original input data. The (K − 1)th, the Ath, the Bth, and the Cth bit positions from the least significant bit in Mask1 are set to "1" while the other bit positions are set to "0."…”

Section: Operation Examples Of the Bmumentioning

confidence: 99%

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Bit Manipulation Accelerator for Communication Systems Digital Signal Processor

Jeong

Sunwoo

2005

EURASIP J. Adv. Signal Process.

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This paper proposes application-specific instructions and their bit manipulation unit (BMU), which efficiently support scrambling, convolutional encoding, puncturing, interleaving, and bit stream multiplexing. The proposed DSP employs the BMU supporting parallel shift and XOR (exclusive-OR) operations and bit insertion/extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 m standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about for scrambling, convolutional encoding, and interleaving compared with existing DSPs.

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Section: Operation Examples Of the Bmumentioning

confidence: 99%

“…Programmable DSPs are greatly improving time-to-market and allowing faster changes and upgrades than hardwired ASIC chips. Hence, the market of ASDSP (application-specific digital signal processor) compromising advantages of both ASIC and DSP is growing [2].…”

Section: Introductionmentioning

confidence: 99%

Bit Manipulation Accelerator for Communication Systems Digital Signal Processor

Jeong

Sunwoo

2005

EURASIP J. Adv. Signal Process.

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“…An ASSP can compromise advantages of custom ASIC chips and general DSP chips [3][4][5][6][7][8]. In other words, an ASSP can adopt high performance and low power of ASIC chips and flexibility of DSP chips.…”

Section: Introductionmentioning

confidence: 99%

SPOCS: Application Specific Signal Processor for OFDM Communication Systems

Baek

Kim

Sunwoo

2008

J Sign Process Syst Sign Image Video Technol

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This paper presents an Application-Specific Signal Processor (ASSP) for Orthogonal Frequency Division Multiplexing (OFDM) Communication Systems, called SPOCS. The instruction set and its architecture are specially designed for OFDM systems, such as Fast Fourier Transform (FFT), scrambling/descrambling, puncturing, convolutional encoding, interleaving/deinterleaving, etc. SPOCS employs the optimized Data Processing Unit (DPU) to support the proposed instructions and the FFT Address Generation Unit (FAGU) to automatically calculate input/output data addresses. In addition, the proposed Bit Manipulation Unit (BMU) supports efficient bit manipulation operations. SPOCS has been synthesized using the SEC 0.18 μm standard cell library and has a much smaller area than commercial DSP chips. SPOCS can reduce the number of clock cycles over 8% 53% for FFT and about 48%~84% for scrambling, convolutional encoding and interleaving compared with existing DSP chips. SPOCS can support various OFDM communication standards, such as Wireless Local Area Network (WLAN), Digital Audio Broadcasting (DAB), Digital Video Broadcasting-Terrestrial (DVB-T), etc.

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“…Therefore, the FAGU must know the number of FFT points and then it can calculate the input data addresses of butterflies. x (4) x (2) x (6) x (1) x (5) x (3) x (7) X(1) …”

Section: Proposed Instructionsmentioning

confidence: 99%

“…With the rapid increase in clock speed it has become feasible to keep the functionality entirely in a programmable DSP, greatly improving time-to-market and allowing faster changes and upgrades [1]. ASDSP can compromise advantages of custom ASIC chips and general DSP chips [1][2][3][4][5]. In other words, ASDSP chips adopt the advantages, such as high performance and low power of ASIC chips and flexibility of DSP chips.…”

Section: Introductionmentioning

confidence: 99%

Application-specific DSP architecture for fast Fourier transform

Heo

Cho

Lee

et al.

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003

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This paper presents ASDSP (Application-Specific Digital Signal Processor) instructions andtheir hardware architecture for high-speed FFT. The proposed instructions calculate a butterfly within two cycles. The proposed architecture employs a Data Processing Unit (DPU) supporting the instructions and an FFT Address Generation Unit (FAGU) automatically calculating the butterfly input and output data addresses. The proposed DPU has a smaller area than commercial DSP chips. Moreover, the number of FFT computation cycles is reduced by the proposed FAGU. The architecture has been modeled by the VHDL. We have used the UMC 0.25@standard cell library for logic synthesis. Performance comparisons show that the number of execution cycles is reduced over 10% and the size of the DPU decreases about 30% compared with Carmel DSP.

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A low-power programmable DSP core architecture for 3G mobile terminals

Cited by 10 publications

References 8 publications

Bit Manipulation Accelerator for Communication Systems Digital Signal Processor

Bit Manipulation Accelerator for Communication Systems Digital Signal Processor

SPOCS: Application Specific Signal Processor for OFDM Communication Systems

Application-specific DSP architecture for fast Fourier transform

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