Bit Manipulation Accelerator for Communication Systems Digital Signal Processor

Abstract

<p/> <p>This paper proposes application-specific instructions and their bit manipulation unit (BMU), which efficiently support scrambling, convolutional encoding, puncturing, interleaving, and bit stream multiplexing. The proposed DSP employs the BMU supporting parallel shift and XOR (exclusive-OR) operations and bit insertion/extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 <inline-formula><graphic file="1687-6180-2005-793614-i1.gif"/></inline-formula>m standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about <inline-formula><graphic file="1687-6180-2005-793614-i2.gif"/></inline-formula> for scrambling, convolutional encoding, and interleaving compared with existing DSPs.</p

Customizing the Datapath and ISA of Soft VLIW Processors

“…PCFs are automatically generated by our processor configuration file generator (PCFGen), which provides a graphical user interface for specifying the architectural Implements 32-bit reverse. SCB Implements a bit scrambling function [18]. PUNC Implements a bit puncturing function [18].…”

“…SCB Implements a bit scrambling function [18]. PUNC Implements a bit puncturing function [18]. SAD16 Implements the 16 × 1 sum of absolute differences function [19].…”

“…The SCB CCU implements a bit scrambling function used in WLAN OFDM modems [18]. It uses two 32-bit inputs, produces a single 32-bit output, and has a latency of eight clock cycles.…”

“…It uses two 32-bit inputs, produces a single 32-bit output, and has a latency of eight clock cycles. The PUNC CCU implements a bit puncturing function, which is also used in the convolutional encoders and interleavers of WLAN OFDM modems [18]. It uses four 32-bit inputs, produces one 32-bit output, and has a latency of 16 clock cycles.…”

Cycle-efficient lineary feedback shift register implementation on word-based micro-architecture

“…To address this problem, one approach would be to implement a LFSR using special purpose hardware [2], [8], [9] which may interface with the host micro-processor via instruction set extensions or interrupt. However, dedicated hardware module is less flexible for applications such as a SDR.…”