A memory window expression to evaluate the endurance of ferroelectric FETs

Hwang

Physica Rapid Research Ltrs

et al. 2021

Owing to their high scalability and superior complementary metal–oxide–semiconductor (CMOS) compatibility, HfO2‐based ferroelectric field‐effect transistors (FeFETs) are proved to be promising candidates for emerging nonvolatile memory devices. However, the poor endurance of these FeFETs, which is attributed to the degradation of the interfacial dielectric layer, is a serious obstacle for commercialization. In FeFETs with a metal–ferroelectric–insulator–semiconductor gate stack, the strong electric field across the interfacial dielectric layer mainly induces charge injection/trapping and limits endurance to <106 cycles. Herein, optimum condition of switching polarization (Pnormals) of ferroelectric materials and a new structural approach to reduce the strength of the electric field across the interfacial dielectric layer and improve memory window (MW) and reliability properties are presented. Based on numerical simulation, it is found that an interfacial electric field increases with Pnormals, and a metal–ferroelectric–metal–insulator–semiconductor FeFET with a 3D channel structure is effective to have high ratio of dielectric capacitance to ferroelectric capacitance, resulting in low electric field through the interfacial layer and large MW.

“…The proposed MFMIS FeFET with the spherical recess channel transistor (hereinafter referred to as MFMIS SR‐FeFET) is applied, as shown in Figure a. The

I_{DS} - V_{GS}

Section: Resultsmentioning

confidence: 99%

“…The

I_{DS}

–

V_{GS}

E_{DE}

, are extracted as a function of the

C_{DE}

C_{FE}

and

P_{normals}

value. This work presents the guideline of gate stack for large MW and high reliability FeFETs.…”

Section: Introductionmentioning

confidence: 99%

High‐Performance and High‐Endurance HfO₂‐Based Ferroelectric Field‐Effect Transistor Memory with a Spherical Recess Channel

Hwang

Physica Rapid Research Ltrs

et al. 2021

“…Therefore, the maximum read memory window is limited to ∼2 V c . [ 44,78 ] As 2 V c of a typical HfO 2 ‐based FE film has a limited range of 2‐4 V, this is far lower than the target value for an FE‐NAND flash device (∼6 V). In particular, a maximum Δ V th of ∼4 V should be achieved for a TLC or QLC drive.…”

Section: Fundamentals Of Fe Film and Fefet Operationmentioning

confidence: 97%

Review of ferroelectric field‐effect transistors for three‐dimensional storage applications

2021

The ferroelectric field‐effect transistor (FeFET) is one of the leading contenders to succeed charge‐trap‐based flash memory (CTF) devices in the current vertically‐integrated NAND flash storage market. The operation of a FeFET is based on the field‐effect in the channel of the FET that is exerted by the uncompensated ferroelectric bound charge, which is also the fundamental source of the depolarization effect. This paper briefly reviews the current status of CTF‐based NAND flash memory as a benchmark for FeFET. Then, a one‐dimensional model based on a load‐line analysis of FeFET technology is presented. The paper subsequently deals with the two‐dimensional domain effect in nano‐sized NAND‐type FeFET devices. While NAND‐type FeFET operation is likely, current ferroelectric materials with high remanent polarization (Pr) of ∼10 μCcm‐2 and coercive field (Ec) of ∼1 MVcm‐1 are not feasible for use in such devices. This is fundamentally due to the high depolarization field induced by the unnecessarily high Pr, which not only destabilizes the memory state but also induces a severe interference effect between neighboring cells. Therefore, a new ferroelectric material with a moderately low Pr and higher Ec > ∼3 MVcm‐1 is necessary, along with structural innovation to minimize the interference effect.

“…Such traps and other types of generated defects are critical and can degrade the memory window during the projected lifetime. Recent studies such as [26], [27] aimed at investigating and modeling the impact of interface and oxide traps on the memory window at both device and system levels, respectively. In addition, charge trapping and detrapping at Si-SiO 2 interface plays an important role in degrading the memory window and it has shown that controlling the charge trapping and the resulting imprinting is necessary in order to ensure the reliability of the FeFET [28].…”

Section: Low-vth Curvementioning

confidence: 99%

FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors

Yayla

Buschjäger

Gupta

et al. 2022

IEEE Trans. Comput.

Ferroelectric FET (FeFET) is a highly promising emerging non-volatile memory (NVM) technology, especially for binarized neural network (BNN) inference on the low-power edge. The reliability of such devices, however, inherently depends on temperature. Hence, changes in temperature during run time manifest themselves as changes in bit error rates. In this work, we reveal the temperature-dependent bit error model of FeFET memories, evaluate its effect on BNN accuracy, and propose countermeasures. We begin on the transistor level and accurately model the impact of temperature on bit error rates of FeFET. This analysis reveals temperature-dependent asymmetric bit error rates. Afterwards, on the application level, we evaluate the impact of the temperature-dependent bit errors on the accuracy of BNNs. Under such bit errors, the BNN accuracy drops to unacceptable levels when no countermeasures are employed. We propose two countermeasures: (1) Training BNNs for bit error tolerance by injecting bit flips into the BNN data, and (2) applying a bit error rate assignment algorithm (BERA) which operates in a layer-wise manner and does not inject bit flips during training. In experiments, the BNNs, to which the countermeasures are applied to, effectively tolerate temperature-dependent bit errors for the entire range of operating temperature.