A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder

Coussy, Philippe; Gnaedig, David; Najkha, A.; Baganne, Adel; Boutillon, Emmanuel; Martin, Éric

doi:10.1109/icassp.2004.1327043

Cited by 4 publications

(7 citation statements)

References 9 publications

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“…However, creating a wrapper component manually is still popular and often the only possible choice. Unfortunately, wrappers increase the final SoC area and decrease system performance [3]. However, most papers do not concentrate on quantitative analysis of the associated performance overheads.…”

Section: Introductionmentioning

confidence: 99%

IP Integration Overhead Analysis in System-on-Chip Video Encoder

Rasmus

Kulmala

Salminen

et al. 2007

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

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Current system-on-chip implementations integrate IP blocks from different vendors. Typical problems are incompatibility and integration overheads. This paper presents a case study of integrating two black-box hardware accelerators into highly scalable and modular multiprocessor system-on-chip architecture. The integration was implemented by creating two wrapper components that adapt the interfaces of the hardware accelerators for the used architecture and on-chip network. The benefit of the accelerators was measured in three different configurations and especially the execution time overheads caused by the software, data delivery, and shared resource contention were extracted and analyzed in MPEG-4 encoder. The overheads increase the function runtime up to 20x compared to the ideal acceleration. In addition, the accelerator that seemed to be more efficient performed worse in practice. As a conclusion, it is pointed out that the integration induces great overhead to the execution time, rendering a-few-clock-cycle optimizations within the accelerator meaningless.

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Section: Introductionmentioning

confidence: 99%

IP Integration Overhead Analysis in System-on-Chip Video Encoder

Rasmus

Kulmala

Salminen

et al. 2007

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

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show abstract

“…Further information about the formal models and the memory design can be found in [10], [12] and [13]. …”

Section: Memory Constraint Graphmentioning

confidence: 99%

“…In [10] and [12], we proposed a SoC design methodology based on algorithmic IP core re-using. Based on high-level synthesis techniques under I/O timing constraints, our approach aims to optimally synthesize the IP by taking into account the system integration constraints: the data rate, technology, bus format, and I/O timing properties specified by timing frames of transfers.…”

Section: Introductionmentioning

confidence: 99%

A More Efficient and Flexible DSP Design Flow from Matlab-Simulink

Coussy¹,

Corre²,

Bomel³

et al.

Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.

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The design of complex Digital Signal Processing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. Unfortunately, the traditional Matlab/ Simulink design flows gather not very flexible hardware blocs. In this paper, we present a methodology and a tool that permit the High-Level Synthesis of DSP applications, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. The efficiency of our approach is demonstrated on the case study of a FFT algorithm.

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“…It will be used during the scheduling process. Further information about the formal models and the memory design can be found in [7], [8], [9].…”

Section: B Memory Constraint Graphmentioning

confidence: 99%

“…In [7] and [8], we proposed a methodology for SoC design that is based on the re-using of algorithmic description. Our approach is based on high-level synthesis techniques under I/O timing constraints and aims to optimally design the corresponding component by taking into account the system integration constraints: the data rate, the technology, and I/O timing properties.…”

Section: Introductionmentioning

confidence: 99%

High-level synthesis under I/O Timing and Memory constraints

Coussy¹,

Corre²,

Bomel³

et al.

2005 IEEE International Symposium on Circuits and Systems

Self Cite

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Abstract-The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm.

show abstract

A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder

Cited by 4 publications

References 9 publications

IP Integration Overhead Analysis in System-on-Chip Video Encoder

IP Integration Overhead Analysis in System-on-Chip Video Encoder

A More Efficient and Flexible DSP Design Flow from Matlab-Simulink

High-level synthesis under I/O Timing and Memory constraints

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