A model for distributed in-network and near-edge computing with heterogeneous hardware

Cooke, Ryan A.; Fahmy, Suhaib A.

doi:10.1016/j.future.2019.11.040

Cited by 21 publications

(14 citation statements)

References 43 publications

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“…Offloading Studies: This category of studies provide resources allocation or task offloading solutions in an edge computing environment that is augmented with in-network computing. While [58], [142], [143] tackle the resource allocation problem with an optimization approach, the study in [144] provides an architecture with the capability of task offloading to an edge processor enhanced with an FPGA accelerator. Ali et al [58] focus on use cases like open-air rock concerts and sports events at which constructing the wired network is not beneficial.…”

Section: B Edge Computingmentioning

confidence: 99%

A Survey on In-Network Computing: Programmable Data Plane and Technology Specific Applications

Kianpisheh

Taleb

2023

IEEE Commun. Surv. Tutorials

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In comparison with cloud computing, edge computing offers processing at locations closer to end devices and reduces the user experienced latency. The new recent paradigm of innetwork computing employs programmable network elements to compute on the path and prior to traffic reaching the edge or cloud servers. It advances common edge/cloud server based computing through proposing line rate processing capabilities at closer locations to the end devices. This paper discusses use cases, enabler technologies and protocols for in-network computing. According to our study, considering programmable data plane as an enabler technology, potential in-network computing applications are in-network analytics, in-network caching, innetwork security, and in-network coordination. There are also technology specific applications of in-network computing in the scopes of cloud computing, edge computing, 5G/6G, and NFV. In this survey, the state of the art, in the framework of the proposed categorization, is reviewed. Furthermore, comparisons are provided in terms of a set of proposed criteria which assess the methods from the aspects of methodology, main results, as well as application-specific criteria. Finally, we discuss lessons learned and highlight some potential research directions.

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Section: B Edge Computingmentioning

confidence: 99%

A Survey on In-Network Computing: Programmable Data Plane and Technology Specific Applications

Kianpisheh

Taleb

2023

IEEE Commun. Surv. Tutorials

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“…The JIT complier can then perform dynamic kernel replication to efficiently exploit overlay resources. Finally, supporting runtime compilation on an embedded processor allows a lightweight edge accelerator node to compile unknown kernels without the need for a powerful server, enabling the emerging trend of in-network FPGA acceleration [43], [44].…”

Section: Background and Related Workmentioning

confidence: 99%

Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation

Jain

Maskell

Fahmy

2022

IEEE Trans. Parallel Distrib. Syst.

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Coarse-grained FPGA overlays built around the runtime programmable DSP blocks in modern FPGAs can achieve high throughput and improved scalability compared to traditional overlays built without detailed consideration of FPGA architecture. These overlays can be mapped to using higher level compilers, achieving fast compilation, software-like programmability and run-time management, and high-level design abstraction. OpenCL allows programs running on a host computer to launch accelerator kernels which can be compiled at run-time for a specific architecture, thus enabling portability. However, prohibitive hardware compilation times in traditional design flows mean that the tools cannot effectively use just-in-time (JIT) compilation or runtime performance scaling on FPGAs. We present a methodology for runtime compilation of dataflow graphs expressed as OpenCL kernels onto coarse-grained overlays. The methodology benefits from the high level of abstraction afforded by using the OpenCL programming model, while the mapping to the overlay significantly reduces compilation and load times. Key characteristics of this work include highly performant DSP-optimized functional units that scale to large overlays on modern devices and the ability to perform automatic resource-aware kernel replication up to the size of the overlay. We demonstrate place and route times orders of magnitude better than traditional HLS flows, even when running on an embedded processor in the Xilinx Zynq.

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“…As these applications grow in scale, this centralized approach leads to bandwidth requirements and potentially impractical computational latencies. This has generated interest in computing wherein processing is in a distributed manner [8].…”

Section: Distributed Processing Systemsmentioning

confidence: 99%

Testing of a Virtualized Distributed Processing System for the Execution of Bio-Inspired Optimization Algorithms

2020

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Due to the stochastic characteristics of bio-inspired optimization algorithms, several executions are often required; then a suitable infrastructure must be available to run these algorithms. This paper reviews a virtualized distributed processing scheme to establish an adequate infrastructure for the execution of bio-inspired algorithms. In order to test the virtualized distributed system, the well known versions of genetic algorithms, differential evolution and particle swarm optimization, are used. The results show that the revised distributed virtualized schema allows speeding up the execution of the algorithms without altering their result in the objective function.

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A model for distributed in-network and near-edge computing with heterogeneous hardware

Abstract: Please refer to published version for the most recent bibliographic citation information. If a published version is known of, the repository item page linked to above, will contain details on accessing it.

Cited by 21 publications

References 43 publications

A Survey on In-Network Computing: Programmable Data Plane and Technology Specific Applications

A Survey on In-Network Computing: Programmable Data Plane and Technology Specific Applications

Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation

Testing of a Virtualized Distributed Processing System for the Execution of Bio-Inspired Optimization Algorithms

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