A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices

Lee, Hyunjin; Ryu, Seong-Wan; Han, Jin−Woo; Yu, L.-E.; lm, Maesoon; Kim, Chimgjin; Kim, Sungho; Lee, Eujime; Kim, Kuk-Hwan; Kim, Ju-Hyun; Bae, Dong-il; Jeon, Sang Cheol; Kim, Kwang Hee; Lee, Gi Sung; Oh, Jae Sub; Park, Yun Chang; Bae, Woo Ho; Yoo, Jaehyun; Yang, J.; Lee, Hee Mok; Choi, Yang‐Kyu

doi:10.1109/vlsit.2007.4339761

Cited by 14 publications

(2 citation statements)

References 1 publication

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“…has been intensively investigated. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19] Because of the tri-gate or gate-all-around structure, strong immunity to the short-channel effect can be attained in NW Tr. In addition, a nondoped channel can be adopted in NW Tr., which is fabricated on a silicon-oninsulator (SOI) wafer, resulting in not only the mobility enhancement due to the reduction in impurity scattering but also the suppression of the variability by suppressing random dopant fluctuations.…”

Section: Introductionmentioning

confidence: 99%

Experimental study of time-dependent dielectric breakdown in tri-gate nanowire transistor

Ota¹,

Tanaka²,

Numata³

et al. 2016

Jpn. J. Appl. Phys.

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We systematically investigate the size dependence of the time-dependent dielectric breakdown (TDDB) in a tri-gate nanowire transistor (NW Tr.). It is newly found that TDDB reliability is degraded in NW Tr. as compared with that in a planar transistor owing to the locally enhanced electric field at the NW corner. Moreover, in the region with a width (W) less than 40 nm, nanowire width reduction leads to a shorter time to gate dielectric breakdown indicating additional degradation of TDDB reliability in NW Tr. with smaller W. Although TDDB in three-dimensional (3D) MOS structures such as a trench MOS capacitor has already been reported, the size dependence of TDDB in scaled NW Tr. is firstly discussed in this paper since a trench capacitor is different from recent NW Tr. in structure, device size, gate dielectric thickness, and scaling effect on TDDB.

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Section: Introductionmentioning

confidence: 99%

Experimental study of time-dependent dielectric breakdown in tri-gate nanowire transistor

Ota¹,

Tanaka²,

Numata³

et al. 2016

Jpn. J. Appl. Phys.

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show abstract

“…have attracted much attention as key device components in future ultralow-power LSI because of their high immunity to short-channel effects. [1][2][3][4] Towards aggressive gate-length scaling down to 10 nm, the diameter of the NW channel must also be reduced to as small as 10 nm. [5][6][7] We have demonstrated high-performance NW Tr.…”

Section: Introductionmentioning

confidence: 99%

Channel size dependence of low-frequency noise in tri-gate silicon nanowire transistors

Saitoh

Ota

Tanaka

et al. 2015

Jpn. J. Appl. Phys.

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We systematically study the channel size dependence of drain current noise amplitude in tri-gate silicon nanowire transistors (NW Tr.) by measuring a large number of samples with various parameters such as gate length (Lg), NW width (WNW), and NW height (HNW) down to 10 nm. The noise of NW Tr. with WNW < 20 nm rapidly increases with 1/WNW because an electron in a single trap on the NW channel blocks the entire current flow (bottleneck effects). The strength of bottleneck effects is determined solely by WNW not by HNW. The noise increase at narrow WNW is smaller in short-Lg Tr. (down to 15 nm).

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Investigation of gate length and fringing field effects for program and erase efficiency in gate-all-around SONOS memory cells

Kim

Choi

Moon

et al. 2013

Solid-State Electronics

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A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices

Cited by 14 publications

References 1 publication

Experimental study of time-dependent dielectric breakdown in tri-gate nanowire transistor

Experimental study of time-dependent dielectric breakdown in tri-gate nanowire transistor

Channel size dependence of low-frequency noise in tri-gate silicon nanowire transistors

Investigation of gate length and fringing field effects for program and erase efficiency in gate-all-around SONOS memory cells

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