A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology

Limachia, Mitesh; Thakker, Rajesh A.; Kothari, Nikhil

doi:10.1016/j.vlsi.2017.11.009

Cited by 17 publications

(18 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…9. The read power reduces drastic cally due to the lower back gate bias which helps in reducing the read power as compared to other cell reported in [25]. This helps in improving its read delay.…”

Section: Resultsmentioning

confidence: 88%

“…The effect has been observed at 0.9V and at the subthreshold supply voltage of 0.4V. The delay at lower voltage has been increased [25]. There is larger variation with respect to variation in temperature.…”

Section: Resultsmentioning

confidence: 91%

“…The write power at 0.9V is 65nW and at 0.4V is 80pW. The write power is very less as compared to projected in [25]. The write metrics for the cell including WSNM and Write power is better as compared to RSNM and read power.…”

Section: Resultsmentioning

confidence: 95%

“…The simulation has been done for super-threshold and sub threshold voltage. Comparison of the proposed work with various SRAM cells reported in [25] for subthreshold operation has been done. Improved results in RSNM during sub-threshold operation.…”

Section: Discussionmentioning

confidence: 99%

“…10T SRAM as shown in Fig. 2 has been proposed in [25] for near threshold having high read and write margins, this paper also has extra virtual ground for improving the stability. The cell works well for super threshold and near threshold but the active power was high .In this paper an 11T SRAM has been proposed for low power applications.…”

Section: B Sram Cellsmentioning

confidence: 99%

See 4 more Smart Citations

FinFET SRAM cell with improved stability and power for low power applications.

Birla

2019

JICS

View full text Add to dashboard Cite

In this paper, a new 11T SRAM cell using Double gate FET (FinFET technology) has been proposed, cell basic component is the 6T SRAM cell with 4 NMOS access transistors to improve the stability over CMOSFET circuits and also makes it a dual port memory cell. The proposed cell also used a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability which helps in reducing the leakage current, active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at threshold and subthreshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV.At subthreshold operation also, it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Impact of process variation on cell stability also been analyzed.

show abstract

Section: Resultsmentioning

confidence: 88%

Section: Resultsmentioning

confidence: 91%

Section: Resultsmentioning

confidence: 95%

Section: Discussionmentioning

confidence: 99%

Section: B Sram Cellsmentioning

confidence: 99%

See 3 more Smart Citations

FinFET SRAM cell with improved stability and power for low power applications.

Birla

2019

JICS

View full text Add to dashboard Cite

show abstract

Design and statistical analysis of low power and high speed 10T static random access memory cell

Prasad¹,

Kumari

Mandi³

et al. 2020

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryStatic random access memory (SRAM)‐based cache memory is an essential part of electronic devices. As the technology node reduces, the power loss and stability has become the major problems. Several SRAM cells had been developed to address the stability and power loss problem. But still, it is a challenge to achieve balance performance among all the parameters of the SRAM cell for sub‐nanometer technology. This paper proposes a novel SRAM cell, which is having comparatively less total, static power loss, less delay, and high stability compared with the conventional cells for 45‐nm complementary metal‐oxide‐semiconductor (CMOS) technology. The total power cost of the proposed 10T cell has been reduced by 90.3%, 85.84%, 51.02%, and 90.9% compared with 6T, N‐controlled (NC), 10T sub, and 10T, respectively. Similarly, the static power cost of the proposed cell has been reduced by 55.17%, 5.72%, ‐41.6%, and 52.9% compared with 6T, NC, 10T‐sub, and 10T, respectively. The proposed cell provides better stability, less delay, and comparable area compared with other considered 10T cells. Finally, the Monte Carlo (MC) simulation and process analysis of SRAM cells validate the efficiency of the proposed 10T cell.

show abstract

Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology

Praveen,

Singh

2024

Circuit Theory & Apps

View full text Add to dashboard Cite

The excessive power usage in modern digital equipment is triggered by memory arrays, mainly including Static Random‐Access Memory (SRAM) chips. Many scientists are working to create an SRAM cell that is fast, highly stable, and uses little power. However, the traditional SRAM cells have instability and read/write failure at scaled technology nodes. This study proposes a Differential Power Schmitt‐Trigger Logic 9 Tcompute SRAM (DPSTL‐9 TCSRAM) cell design with high read‐and‐write stability and low energy consumption. In SRAM cells, the sensing amplifier (SA), pre‐charge circuit, row decoder, and column decoder are the primary operational elements. Through the use of a single‐bitline (SBL) configuration and a one‐sided Schmitt‐trigger (ST) inverter (STI), the proposed deisgn cell achieves an outstanding read stability performance. In this work, the differential Power Generation (DPG) technique is employed to improve the architecture's writing capacity. The standard AND gates are combined with Schmitt‐trigger logic AND gates to improve noise tolerance while consuming less power and taking up less space. Instead of using a power‐gating mechanism, this research focuses on modifying a power delay product (PDP) circuit to increase the cell's read‐and‐write operation efficiency. The modified decoupled SA plays a major role in the access time and provides significant benefits in terms of read latency. Tanner EDA Tool platform version 16.0 can be used to execute the specified design. The performance metrics of stability, area, latency, and power analysis are examined, and also, the Monte Carlo simulation and reliability simulation are conducetd to show the efficacy of the proposed design.

show abstract

A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology

Cited by 17 publications

References 25 publications

FinFET SRAM cell with improved stability and power for low power applications.

FinFET SRAM cell with improved stability and power for low power applications.

Design and statistical analysis of low power and high speed 10T static random access memory cell

Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology

Contact Info

Product

Resources

About