A new approach for improving operating margin of unipolar ReRAM using local minimu m of reset voltage

“…In order to be compatible with the CMOS process many groups have focused on the oxides of metals already used in mass production, such as CuO x [57], CuSiO x [58], TaO x /TiO x [59], NiO x [60], HfO x [61], and WO x [62]. Here we use WO x as an example to discuss the switching characteristics and mechanisms.…”

Section: Tmo Rerammentioning

confidence: 99%

“…ReRAM primarily operates in bipolar mode, but unipolar operation of TMO devices has been multiply reported [59,63]. Unipolar operation may be achieved by two methods: 1) by using two different program voltages; or 2) by using different pulse durations.…”

Section: Unipolar Operation and 3d Stacking Of Rerammentioning

confidence: 99%

State-of-the-art flash memory devices and post-flash emerging memories

Lue

Chen

2011

Sci. China Inf. Sci.

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Although conventional Floating gate (FG) flash memory has recently gone into the 2X nm node, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (multi-level cell, or more than one bit storage per cell) storage. However, due to the simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels), CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1Xnm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues. Devices that do not rely on charge storage are naturally not limited by the number of electrons, thus promise further scaling below 10 nm. Several of the most promising post-flash era devices, their operation principle and critical issues are reviewed. (One of them, phase change memory, will be covered in a separate article thus not included here.) Their potential applications and challenges for 3D stacking are critically examined. State-of-the-art floating gate flash memoryFlash memories have become ubiquitous in consumer electronics, mobile devices and PC and enterprise applications [1]. The basic operation principle of flash memory device is to store electrons in a floating gate (FG) or a charge-trapping layer (such as SONOS) and accordingly the Vth of the MOSFET devices is changed and identified as the stored logic state. The older EEPROM (electrically erasable and programmable read only memory) uses two transistors to provide RAM-like random access and bit alterable features. Flash memory gives up the bit alterable feature and adopts a block erase (flash) to achieve a 1-transistor (1T) cell that allows much higher density. Over the years, the array architecture has converged into NOR and NAND types (Figure 1) for different applications.NOR Flash device uses channel hot electron (CHE) injection for programming and has retained fast random access capability suitable for code storage applications. The random access feature requires a

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“…3 presents a list of recent developments in resistive memory (ReRAM) macros [37]- [46]. Logic-process-compatible one-transistor-one-memristor (1T1M or 1T1R) cells [38]- [44], [47]- [52] are appropriate for embedded NVM (eNVM) applications, which require fast random read access and a low minimum supply voltage (VDD) for read operations. Three-dimensional cross-point [45], [46], [53]- [56] and buried-wordline-selector [37] memristive memory devices are suitable for low-cost, ultra-high capacity applications due to their tolerance for high read-VDDmin and slow read access time.…”

Section: Introductionmentioning

confidence: 99%

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Chang

Lee

Chen

et al. 2015

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Memristive devices have shown considerable promise for on-chip nonvolatile memory and computing circuits in energyefficient systems. However, this technology is limited with regard to speed, power, VDDmin, and yield due to process variation in transistors and memrisitive devices as well as the issue of read disturbance. This paper examines trends in the design of device and circuits for on-chip nonvolatile memory using memristive devices as well as the challenges faced by researchers in its further development. Several silicon-verified examples of circuitry are reviewed in this paper, including those aimed at high-speed, area-efficient, and low-voltage applications.Index Terms-Memristive device, memristor, nonvolatile memory, recent developments in resistive memory (ReRAM), resistive RAM.

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A new approach for improving operating margin of unipolar ReRAM using local minimu m of reset voltage

Cited by 19 publications

References 1 publication

Challenges and opportunities for HfO<inf>X</inf> based resistive random access memory

Challenges and opportunities for HfO<inf>X</inf> based resistive random access memory

State-of-the-art flash memory devices and post-flash emerging memories

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

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