A new aspect on mechanical stress effects in scaled MOS devices

Hamada, A.; Furusawa, Takeshi; Takeda, Eiji

doi:10.1109/vlsit.1990.111034

Cited by 27 publications

(11 citation statements)

References 4 publications

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“…Specific stress charac- teristics are commonly used to promote the performance of Si MOSFETs, and such "strained-Si" technology has been implemented in manufacturing of high-performance microprocessors since the 90-nm technology node in 2002 [16]- [21]. For this purpose, Ge is implanted into the source/drain region for the pMOS devices and a silicon nitride capping layer is applied for the nMOSFETs [22].…”

Section: A Piezoresistivity Effect Of Simentioning

confidence: 99%

Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

Ryu

Jiang

et al. 2012

IEEE Trans. Device Mater. Relib.

108

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Abstract-Three-dimensional (3-D) integration with throughsilicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in the TSV structures can affect the device performance by degrading carrier mobility and raise serious reliability concerns. In this paper, the effect of thermal stresses in TSV structures on carrier mobility and keep-out zone (KOZ) was investigated by focusing on the characteristics of the stresses near the surface where the electronic devices are located. The near-surface stresses were characterized by finite element analysis, and the stress effect on carrier mobility was evaluated by considering the piezoresistivity effect near the Si surface. In this paper, the elastic anisotropy of Si was taken into account to evaluate the effect on carrier mobility for both n-and p-channel MOSFET devices aligned along the [100] and [110] directions. The results showed a significant stress effect on carrier mobility, particularly for n-type Si with [100] device alignment and p-type Si with [110] device alignment. Based on these results, the dimension of the KOZ was estimated based on a criterion of 5% change in the carrier mobility. Finally, the effects due to stress interactions in a TSV array and plasticity in Cu vias on the KOZ were investigated. The effect of stress interaction was found to depend on the ratio of the pitch to diameter of the TSV array. When this ratio is less than 5, the stress interaction can increase the size of the KOZ. In contrast, the via material plasticity was found to be useful in reducing the stress level and hence the size of the KOZ.Index Terms-Finite element analysis (FEA), keep-out zone (KOZ), thermomechanical reliability, through-silicon via (TSV), three-dimensional interconnects.

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Section: A Piezoresistivity Effect Of Simentioning

confidence: 99%

Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

Ryu

Jiang

et al. 2012

IEEE Trans. Device Mater. Relib.

108

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show abstract

“…This has been attributed to the existence of parasitic series resistances [17]. The effect of parasitic resistances are more prominent for shorter channel length TFTs since their channel resistance is smaller [18]. Longitudinal tensile strain increases the parasitic resistances [12] and makes them even more pronounced for TFTs of shorter channel length.…”

Section: Resultsmentioning

confidence: 99%

Effects of mechanical strain on laser crystallized polysilicon thin film transistors and ring oscillators fabricated on stainless steel foil

Jamshidi-Roudbari

Kuo

Hatalis

2008

Solid-State Electronics

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“…A four-point bending technique was used to expose the device under test (DUT) to a controlled and uniform tensile uniaxial stress [7][8][9]. Stress was controlled by adjusting the deflection at the ends of the strip, thus enforcing a defined bending radius.…”

Section: Stress Apparatus and Measurement Proceduresmentioning

confidence: 99%