A new efficient method for the transient simulation of three-dimensional interconnect structures

Kumashiro, S.; Rohrer, R.A.; Strojwas, Andrzej J.

doi:10.1109/iedm.1990.237195

Cited by 28 publications

(13 citation statements)

References 2 publications

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“…For the substrate problem, these methods pose serious challenges. With FDM, a uniformly discretized mesh is used [5], [13], therefore incurring substrate overmeshing which yields unnecessarily dense grids far from contact sources. Thus, although this method leads to a straightforward resistor network, the resulting matrix sizes are prohibitive due to the substrate size which becomes a real bottleneck.…”

Section: Introductionmentioning

confidence: 99%

Accurate Substrate Analysis Based on a Novel Finite Difference Method via Synchronization Method on Layered and Adaptive Meshing

Han

Zhao

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, we present a finite difference method (FDM) based on layered and adaptive meshing to extract substrate resistance. To allow adaptive meshing, a novel synchronization method is introduced which expresses the potential at other points than the centroids of panels by modifying the finite difference equations. This method makes it possible to overcome the high computational cost of the FDM due to tight uniform meshing requirements while enjoying a straightforward implementation and easy handling of irregular/arbitrary substrate structures to extract the substrate coupling of integrated circuits.Index Terms-Combined FDM/FEM, finite difference method, isolation, pulse basis, Rao-Wilton-Glisson basis, substrate analysis, synchronization method.

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Section: Introductionmentioning

confidence: 99%

Accurate Substrate Analysis Based on a Novel Finite Difference Method via Synchronization Method on Layered and Adaptive Meshing

Han

Zhao

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…When analyzing high-performance integrated circuit designs, it is well known that the single lumped resistor-capacitor (RC) model of interconnect is insufficiently accurate. For analysis (or simulation), research has been carried out of the use of model order reduction (MOR) [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

Static Superelement Technique based Macromodeling for High Speed Nano Designs

Ravindra

Srinivas

2008

2008 8th IEEE Conference on Nanotechnology

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This paper presents a model order reduction technique based on static super-element technique for high speed coupled integrated circuit interconnects in nanometer designs. The salient feature of this technique is less complexity in computation of a few smallest poles of the reduced order model. This paper shows that the static super-element technique produces reduced systems that accurately follow the time and frequency-domain responses of the original system. All the experiments have been carried out using Cadence Design Simulator which indicate that the proposed technique achieves more accuracy with less CPU time than the other model order reduction techniques existing in literature.

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“…It has proposed in [16] for parametric interconnect analysis. SBT been shown [1] that reasonably accurate electro-quasistatic, technique [17] is proposed for tightly coupled interconnects or transient interconnect, simulations could be performed by with process variations. All these methods pose specific ascomputing the time evolution of the electric field both inside sumptions on the models, and their potential for general appliand outside the conductors via a finite-difference discretiza-cations is limited.…”

mentioning

confidence: 99%

Generating Reduced Order Models for High Speed VLSI Interconnects using Balancing-Free Square Root Method

Ravindra

Srinivas

2008

2008 12th IEEE Workshop on Signal Propagation on Interconnects

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This paper presents a model order reduction tech-Such reduced-order models can be used to predict the timenique based on balancing-free square root (BSR) method for domain or frequency-domain response of the linear network.high speed coupled integrated circuit interconnects. The salient A multipoint moment-matching or complex frequency hopping features of this technique are the less CPU time resulting from the passivity of the reduced transfer function, and the (CFH) technique extracts accurate dominant poles of a linear availability of provable weighted error bounds for the reduced-sub-network up to any predefined maximum frequency. This order system. This paper shows that the balancing-free square method generates a single transfer function for a large linear root method produces reduced systems that accurately follow sub-network and provides for a CPU/accuracy tradeoff. Model the time-and frequency-domain responses of the original order reduction can also be obtained using projecting the system. All the experiments have been carried out using Cadence Design Simulator which indicate that the proposed BSR achieves origial system described by nonlinear differential equations more accuracy with less CPU time than the other model order into krylov subspace of lower dimension. This reduced model reduction techniques existing in literature.can be simulated using conventional numerical techniques. Simulation of interconnects can also be performed treating

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A new efficient method for the transient simulation of three-dimensional interconnect structures

Cited by 28 publications

References 2 publications

Accurate Substrate Analysis Based on a Novel Finite Difference Method via Synchronization Method on Layered and Adaptive Meshing

Accurate Substrate Analysis Based on a Novel Finite Difference Method via Synchronization Method on Layered and Adaptive Meshing

Static Superelement Technique based Macromodeling for High Speed Nano Designs

Generating Reduced Order Models for High Speed VLSI Interconnects using Balancing-Free Square Root Method

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